參數(shù)資料
型號： K4J52324KI-HC1A0
元件分類： DRAM
英文描述： 512M X 1 DDR DRAM, 0.2 ns, PBGA136
封裝： HALOGEN FREE AND ROHS COMPLIANT, FBGA-136
文件頁數(shù)： 37/61頁
文件大?。?/td> 1364K
代理商： K4J52324KI-HC1A0
- 42 -
K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
NOTE : 1. DI b = data-in for column b.
2. Three subsequent elements of data-in the programmed order following DI b.
3. A burst of 4 is shown.
4. tCDLR is referenced from the first positive CK edge after the last data-in pair.
5. The READ and WRITE commands are to the same device. However, the READ and WRITE commands may be to different devices, in which case tCDLR is not
required and the READ command could be applied earlier.
6. A8 is LOW with the WRITE command (auto precharge is disabled).
7. WRITE latency is set to 3
Figure 21. WRITE to READ
DON’T CARE
TRANSITIONING DATA
NOP
WRITE
T0
T1
T3
T3n
T4
T5
CK
COMMAND
ADDRESS
Bank
Col b
tDQSS
NOP
T4n
T6
DQ
DM
WDQS
T2
T10
READ
DI
b
T17
T18
NOP
tDQSS (NOM)
Bank a.
Col n
CL = 8
RDQS
tDQSS
DQ
DM
WDQS
DI
b
DO
n
tDQSS (MIN)
CL = 8
RDQS
DO
n
tDQSS
DQ
DM
WDQS
DI
b
DO
n
tDQSS (MAX)
CL = 8
RDQS
tCDLR = 5
T18n
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K4J52324QC 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:512Mbit GDDR3 SDRAM
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K4J52324QC-BC14000 制造商:Samsung Semiconductor 功能描述:GDDR3 SDRAM X32 BOC LEAD PART 10W - Trays
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