參數(shù)資料
型號(hào)： K4J52324KI-HC1A0
元件分類： DRAM
英文描述： 512M X 1 DDR DRAM, 0.2 ns, PBGA136
封裝： HALOGEN FREE AND ROHS COMPLIANT, FBGA-136
文件頁數(shù)： 52/61頁
文件大小： 1364K
代理商： K4J52324KI-HC1A0
- 56 -
K4J52324KI
datasheet
GDDR3 SGRAM
Rev. 1.2
NOTE : 1. The WRITE latency can be set from 1 to 7 clocks. When the WRITE latency is set to 1 or 2 or 3 clocks, the input buffers are turned on during the
ACTIVE commands reducing the latency but added power. When the WRITE latency is set to 5 ~7 clocks which must be greater than 7ns, the
input buffers are turned on during the WRITE commands for lower power operation.
2. A low to high transition on the WDQS line is not allowed in the half clock prior to the write preamble.
3. The last rising edge of WDQS after the write postamble must be driven high by the controller. WDQS can not be pulled high by
the on-die termination alone.
4. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific
voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ).
5. The cycle to cycle jitter over 1~6 cycle short term jitter
Parameter
Symbol
-HC12(800MHz)
-HC14(700MHz)
Unit
NOTE
Min
Max
Min
Max
DQS out access time from CK
tDQSCK
-0.23
+0.23
-0.26
+0.26
ns
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
CK cycle time
CL=11
tCK
1.25
3.3
-
3.3
ns
CL=10
1.4
ns
WRITE Latency
tWL
1,2,3,6,7
-
1,2,3,5,6,7
-
tCK
1
DQ and DM input hold time relative to DQS
tDH
0.16
-
0.18
-
ns
DQ and DM input setup time relative to DQS
tDS
0.16
-
0.18
-
ns
Active termination setup time
tATS
10
-
10
-
ns
Active termination hold time
tATH
10
-
10
-
ns
DQS input high pulse width
tDQSH
0.48
0.52
0.48
0.52
tCK
DQS input low pulse widthl
tDQSL
0.48
0.52
0.48
0.52
tCK
Data strobe edge to Dout edge
tDQSQ
-0.140
0.140
-0.160
0.160
ns
DQS read preamble
tRPRE
0.4
0.6
0.4
0.6
tCK
DQS read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Write command to first DQS latching transition
tDQSS
WL-0.2
WL+0.2
WL-0.2
WL+0.2
tCK
DQS write preamble
tWPRE
0.35
-
0.4
0.6
tCK
2
DQS write preamble setup time
tWPRES
0
-
0
-
ns
DQS write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
3
Half strobe period
tHP
tCLmin or
tCHmin
-
tCLmin or
tCHmin
-tCK
Data output hold time from DQS
tQH
tHP-0.14
-
tHP-0.16
-ns
Data-out high-impedance window
from CK and CK
tHZ
-0.3
-
-0.3
-
ns
4
Data-out low-impedance window from
CK and CK
tLZ
-0.3
-
-0.3
-
ns
4
Address and control input hold time
tIH
0.3
-
0.35
-
ns
Address and control input setup time
tIS
0.3
-
0.35
-
ns
Address and control input pulse width
tIPW
0.9
-
1.0
-
ns
Jitter over 1~6 clock cycle error
tJ
-
0.03
-
0.03
tCK
5
Cycle to cycle duty cycle error
tDCERR
-
0.03
-
0.03
tCK
Rise and fall times of CK
tR, tF
-
0.2
-
0.2
tCK
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