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參數(shù)資料
| 型號(hào)： | LXT386 |
| 廠商： | Intel Corp. |
| 英文描述： | QUAD T1/E1/J1 Transceiver |
| 中文描述： | 四T1/E1/J1收發(fā)器 |
| 文件頁數(shù)： | 12/78頁 |
| 文件大?。?/td> | 500K |
| 代理商： | LXT386 |
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LXT386
—
QUAD T1/E1/J1 Transceiver
12
Datasheet
F3
F2
F1
G3
88
87
86
85
A3
A2
A1
A0
DI
DI
DI
DI
Protected Monitoring/Address Select Inputs.
Hardware Mode
In hardware mode these pins are used to select a specific port for non
intrusive monitoring. During protection monitoring receiver 0 inputs are
internally connected to a specific transmit or receive port. Receiver 0
routes the data from the selected port to its data and clock recovery
circuits. The data on the monitor port can be routed to TTIP0/TRING0 by
activating the remote loopback for channel 0 (TCLK0 must be active in
order for this operation to take place). In addition, the recovered clock and
data can be observed at the RCLK0/RPOS0/RNEG0 outputs.
If A0-A3 are Low, the LXT386 is configured as a quad line transceiver
without monitoring capability.
Transmitter monitoring is not supported when the respective channel is set
to analog loopback mode.
Host Mode
In non-multiplexed host mode, these pins function as non-multiplexed
address pins.
Table 1. Pin Assignments and Signal Descriptions
(Continued)
Ball #
PBGA
Pin #
LQFP
Symbol
I/O
1
Description
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
2. N/C means
“
Not Connected
”
A3
A2
A1
A0
Selection
0
0
0
0
No Protection Monitoring
0
0
0
1
Receiver 1
0
0
1
0
Receiver 2
0
0
1
1
Receiver 3
0
1
0
0
Reserved
0
1
0
1
Reserved
0
1
1
0
Reserved
0
1
1
1
Reserved
1
0
0
0
No Protection Monitoring
1
0
0
1
Transmitter 1
1
0
1
0
Transmitter 2
1
0
1
1
Transmitter 3
1
1
0
0
Reserved
1
1
0
1
Reserved
1
1
1
0
Reserved
1
1
1
1
Reserved
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