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參數(shù)資料
| 型號(hào)： | LXT386 |
| 廠商： | Intel Corp. |
| 英文描述： | QUAD T1/E1/J1 Transceiver |
| 中文描述： | 四T1/E1/J1收發(fā)器 |
| 文件頁(yè)數(shù)： | 40/78頁(yè) |
| 文件大?。?/td> | 500K |
| 代理商： | LXT386 |
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LXT386
—
QUAD T1/E1/J1 Transceiver
40
Datasheet
Table 10. Remote Loopback Register, RLOOP (02H)
Bit
Name
Function
3-0
RL3-RL0
Setting a bit to
“
1
”
enables remote loopback for transceivers 3-0 respectively.
Table 11. TAOS Enable Register, TAOS (03H)
Bit
1
Name
Function
2
3-0
TAOS3-TAOS0
Setting a bit to
“
1
”
causes a continuous stream of marks to be sent out at the TTIP and
TRING pins of the respective transceiver 3-0.
7-4
-
Write
“
0
”
to these positions for normal operation.
1. On power up all register bits are set to
“
0
”
.
2. MCLK is used as timing reference. If MCLK is not available then the channel TCLK is used as the reference. This feature is
not available in data recovery and line driver mode (MCLK= High and TCLK = High)
Table 12. LOS Status Monitor Register, LOS (04H)
Bit
1
Name
Function
3-0
LOS3-LOS0
Respective bit(s) are set to
“
1
”
every time the LOS processor detects a valid loss of signal
condition in transceivers 3-0.
1. On power up all register bits are set to
“
0
”
. Any change in the state causes an interrupt. All LOS interrupts are cleared by a
single read operation.
Table 13. DFM Status Monitor Register, DFM (05H)
Bit
1
Name
Function
3-0
DFM3-DFM0
Respective bit(s) are set to
“
1
”
every time the short circuit monitor detects a valid
secondary output driver short circuit condition in transceivers 3-0. Note that DFM is
available only in configurations with no transmit series resistors (T1 mode with
TVCC=3.3V).
1. On power-up all the register bits are set to
“
0
”
. All DFM interrupts are cleared by a single read operation.
Table 14. LOS Interrupt Enable Register, LIE (06H)
Bit
1
Name
Function
3-0
LIE3-LIE0
Transceiver 3-0 LOS interrupts are enabled by writing a
“
1
”
to the respective bit.
7-4
-
Write
“
0
”
to these positions for normal operation.
1. On power-up all the register bits are set to
“
0
”
and all interrupts are disabled.
Table 15. DFM Interrupt Enable Register, DIE (07H)
Bit
1
Name
Function
3-0
DIE3-DIE0
Transceiver 3-0 DFM interrupts are enabled by writing a
“
1
”
to the respective bit.
7-4
-
Write
“
0
”
to these positions for normal operation.
1. On power-up all the register bits are set to
“
0
”
and all interrupts are disabled.
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