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參數(shù)資料
| 型號： | LXT386 |
| 廠商： | Intel Corp. |
| 英文描述： | QUAD T1/E1/J1 Transceiver |
| 中文描述： | 四T1/E1/J1收發(fā)器 |
| 文件頁數(shù)： | 43/78頁 |
| 文件大?。?/td> | 500K |
| 代理商： | LXT386 |
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QUAD T1/E1/J1 Transceiver
—
LXT386
Datasheet
43
Table 24. Pulse Shaping Indirect Address Register, PSIAD (10H)
Bit
1
Name
Function
0-2
LENAD 0-2
The three bit value written to these bits determine the channel to be addressed:
0H = channel 0
1H = channel 1
2H = channel 2
3H = channel 3
Data can be read from (written to) the Pulse Shaping Data Register (PSDAT).
3 - 7
-
Reserved.
1. On power-on reset the register is set to
“
0
”
.
Table 25. Pulse Shaping Data Register, PSDAT (11H)
Bit
Name
Function
0-2
LEN 0-2
1, 3
LEN0-2 determine the LXT386 operation mode: T1 or E1. In addition, for T1 operation,
LEN2-0 set the pulse shaping to meet the T1.102 pulse template at the DSX-1 cross-
connect point for various cable lengths:
LEN2
LEN1
LEN0
Line Length
Cable Loss
2
Operation
Mode
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0 - 133 ft. ABAM
133 - 266 ft. ABAM
266 - 399 ft. ABAM
399 - 533 ft. ABAM
533 - 655 ft. ABAM
0.6 dB
1.2 dB
1.8 dB
2.4 dB
3.0 dB
T1
0 0 0
E1 G.703, 75
coaxial cable and 120
twisted pair cable.
E1
3 - 7
-
Reserved.
1. On power-on reset the register is set to
“
0
”
.
2. Maximum cable loss at 772 KHz.
3. When reading LEN, bit values appear inverted.
“
B1
”
revision silicon will fix this so the bits read back correctly.
Table 26. Output Enable Register, OER (12H)
Bit
1
Name
Function
3-0
OE3 - OE0
Setting a bit to
“
1
”
tristates the output driver of the corresponding transceiver.
1. On power-up all the register bits are set to
“
0
”
.
Table 27. AIS Status Monitor Register, AIS (13H)
Bit
1
Name
Function
3-0
AIS3-AIS0
Respective bit(s) are set to
“
1
”
every time the receiver detects a AIS condition in
transceivers 3-0.
1. On power-up all the register bits are set to
“
0
”
. All AIS interrupts are cleared by a single read operation.
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