參數(shù)資料
型號(hào)： LXT386
廠商： Intel Corp.
英文描述： QUAD T1/E1/J1 Transceiver
中文描述： 四T1/E1/J1收發(fā)器
文件頁數(shù)： 64/78頁
文件大?。?/td> 500K
代理商： LXT386
LXT386
—
QUAD T1/E1/J1 Transceiver
64
Datasheet
Valid write signal pulse width
Tvwr
60
–
–
ns
Inactive write to inactive INT delay time
Tint
–
–
10
ns
Chip select to RDY delay time
3
Tdrdy
0
–
12
ns
Active ready Low time
Tvrdy
–
–
40
ns
Inactive ready to tri-state delay time
3
Trdyz
–
–
3
ns
Figure 23. Non-Multiplexed Intel Mode Write Timing
Table 47. Intel Mode Write Timing Characteristics
(Continued)
Parameter
2
Sym
Min
Typ
1
Max
Unit
Test Conditions
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
2. C
= 100pF on D0-D7, all other outputs are loaded with 50pF.
3. These times don
’
t apply for Reset Register 0Ah, since RDY line goes low once during the cycle. Please refer to Reset
Operation and Host Mode sections for more information.
A4-A0
ALE
D7-D0
RDY
Tristate
Tristate
ADDRESS
CS
WR
INT
tSCSW
tVWR
tDRDY
tVRDY
tHCSW
WRITE DATA
tSDW
tHDW
tINT
tDRDY
tRDYZ
(pulled High)
tSAW
tHAW
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