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參數資料
| 型號： | LXT386 |
| 廠商： | Intel Corp. |
| 英文描述： | QUAD T1/E1/J1 Transceiver |
| 中文描述： | 四T1/E1/J1收發(fā)器 |
| 文件頁數： | 30/78頁 |
| 文件大?。?/td> | 500K |
| 代理商： | LXT386 |
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LXT386
—
QUAD T1/E1/J1 Transceiver
30
Datasheet
3.6
Jitter Attenuation
A digital Jitter Attenuation Loop (JAL) combined with a FIFO provides Jitter attenuation. The JAL
is internal and requires no external crystal nor high-frequency (higher than line rate) reference
clock.
In Host Mode, the Global Control Register (GCR) determines whether the JAL is positioned in the
receive or transmit path. In Hardware Mode, the JAL position is determined by the JASEL pin.
The FIFO is a 32 x 2-bit or 64 x 2-bit register (selected by the FIFO64 bit in the GCR). Data is
clocked into the FIFO with the associated clock signal (TCLK or RCLK), and clocked out of the
FIFO with the dejittered JAL clock. See
Figure 8
. When the FIFO is within two bits of overflowing
or underflowing, the FIFO adjusts the output clock by
1/8
of a bit period. The Jitter Attenuator
produces a constant delay of 17 or 33 bits in the associated path (refer to test specifications). This
feature can be used for hitless switching applications. This advanced digital jitter attenuator meets
latest jitter attenuation specifications. See
Table 3
.
Under software control, the low limit jitter attenuator corner frequency depends on FIFO length
and the JACF bit setting (this bit is in the GCR register). In Hardware Mode, the FIFO length is
fixed to 64 bits. The corner frequency is fixed to 6 Hz for T1 mode and 3.5 Hz for E1 mode.
Table 3. Jitter Attenuation Specifications
T1
E1
AT&T Pub 62411
ITU-T G.736
GR-253-CORE
1
ITU-T G.742
3
TR-TSY-000009
2
ITU-T G.783
4
ETSI CTR12/13
BAPT 220
1. Category I, R5-203.
2. Section 4.6.3.
3. Section 6.2 When used with the SXT6234 E2-E1 mux/demux.
4. Section 6.2.3.3 combined jitter when used with the SXT6251 21E1 mapper.
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