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參數(shù)資料
| 型號(hào)： | LXT386 |
| 廠商： | Intel Corp. |
| 英文描述： | QUAD T1/E1/J1 Transceiver |
| 中文描述： | 四T1/E1/J1收發(fā)器 |
| 文件頁(yè)數(shù)： | 50/78頁(yè) |
| 文件大小： | 500K |
| 代理商： | LXT386 |
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LXT386
—
QUAD T1/E1/J1 Transceiver
50
Datasheet
5.5
Device Identification Register (IDR)
The IDR register provides access to the manufacturer number, part number and the LXT386
revision. The register is arranged per IEEE 1149.1 and is represented in
Table 31
. Data into the IDR
is shifted in LSB first.
5.5.1
Bypass Register (BYR)
The Bypass Register is a 1 bit register that allows direct connection between the TDI input and the
TDO output.
5.5.2
Analog Port Scan Register (ASR)
The ASR is a 5 bit shift register used to control the analog test port at pins AT1, AT2. When the
INTEST_ANALOG instruction is selected, TDI connects to the ASR input and TDO connects to
the ASR output. After 5 TCK rising edges, a 5 bit control code is loaded into the ASR. Data into
the ASR is shifted in LSB first.
Table 32
shows the 8 possible control codes and the corresponding operation on the analog port.
The Analog Test Port can be used to verify continuity across the coupling transformers primary
winding.
The Analog Test Port can be used to verify continuity across the coupling transformer
’
s primary
winding as shown in
Figure 17
. By applying a stimulus to the AT1 input, a known voltage will
appear at AT2 for a given load. This, in effect, tests the continuity of a receive or transmit interface.
RPOS0
O
RPOS0
N/A
-
HIZ0
HIZ0 controls the RPOS0, RNEG0 and RCLK0 pins. Setting HIZ0 to
“
0
”
enables output on the pins. Setting HIZ0 to
“
1
”
tristates the pins.
RNEG0
O
RNEG0
LOS0
O
LOS0
Example 1. Boundary Scan Register (BSR) (Continued)
Bit #
Pin
Signal
I/O
Type
Bit
Symbol
Comments
Table 31. Device Identification Register (IDR)
Bit #
Comments
31 - 28
Revision Number
27 - 12
Part Number
11 - 1
Manufacturer Number
0
Set to
“
1
”
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