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參數(shù)資料
| 型號(hào)： | LXT386 |
| 廠商： | Intel Corp. |
| 英文描述： | QUAD T1/E1/J1 Transceiver |
| 中文描述： | 四T1/E1/J1收發(fā)器 |
| 文件頁數(shù)： | 26/78頁 |
| 文件大?。?/td> | 500K |
| 代理商： | LXT386 |
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LXT386
—
QUAD T1/E1/J1 Transceiver
26
Datasheet
Each output driver is supplied by a separate power supply (TVCC and TGND). The transmit pulse
shaper is bypassed if no MCLK is supplied while TCLK is pulled high. In this case TPOS and
TNEG control the pulse width and polarity on TTIP and TRING. With MCLK supplied and TCLK
pulled high the driver enters TAOS (Transmit All Ones pattern). Note that the TAOS generator uses
MCLK as a timing reference. In order to assure that the output frequency is within specification
limits, MCLK must have the applicable stability.TAOS is inhibited during Remote Loopback.
3.3.1
Transmit Pulse Shaping
The transmitted pulse shape is internally generated using a high speed D/A converter. Shaped
pulses are further applied to the line driver for transmission onto the line at TTIP and TRING. The
line driver provides a constant low output impedance regardless of whether it is driving marks,
spaces or if it is in transition. This well controlled dynamic impedance provides excellent return
loss when used with external precision resistors (± 1% accuracy) in series with the transformer.
3.3.1.1
Hardware Mode
In hardware mode, pins LEN0-2 determine the pulse shaping as described in
Table 2
. The LEN
settings also determine whether the operating mode is T1 or E1. Note that in T1 operation mode, all
four ports will share the same pulse shaping setting. Independent pulse shaping for each channel is
available in host mode
3.3.1.2
Host Mode
In Host Mode, the contents of the Pulse Shaping Data Register (PSDAT) determines the shape of
pulse output at TTIP/TRING. Refer to
Table 24
and
Table 25
.
Figure 6. 50% AMI Encoding
TTIP
TRING
1
0
1
Bit Cell
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