參數(shù)資料
型號: LXT386
廠商: Intel Corp.
英文描述: QUAD T1/E1/J1 Transceiver
中文描述: 四T1/E1/J1收發(fā)器
文件頁數(shù): 7/78頁
文件大小: 500K
代理商: LXT386
QUAD T1/E1/J1 Transceiver
LXT386
Datasheet
7
1.0
Features
Single rail 3.3V supply with 5V tolerant inputs
Low power consumption of 150mW per channel (typical)
Superior crystal-less jitter attenuator
Meets ETSI CTR12/13, ITU G.736, G.742, G.823 and AT&T Pub 62411 specifications
Optimized for SONET/SDH applications, meets ITU G.783 mapping jitter specification
Constant throughput delay jitter attenuator
Hitless Protection Switching (HPS) for 1 to 1 protection without relays
HDB3, B8ZS, or AMI line encoder/decoder
Provides protected monitoring points per ITU G.772
Analog/digital and remote loopback testing functions
LOS per ITU G.775, ETS 300 233 and T1.231
8 bit parallel or 4 wire serial control interface
Hardware and Software control modes
JTAG Boundary Scan test port per IEEE 1149.1
160 PBGA and 100 pin LQFP packages
Figure 1. LXT386 Block Diagram
HARDWARE / SOFTWARE CONTROL
(JTAG INTERFACE)
A
DATA SLICER
LINE DRIVER
G
PULSE
MCLK
LOS
LOS
CLCLOCK
RECOVERY
PULSE
SHAPER
D
R
TPOS
TCLK
TNEG
RPOS
RCLK
RNEG
0
1
2
3
B8ZS / HDB3
DECODER
B8ZS / HDB3
ENCODER
JITTER
ATTENUATOR
RX OR TX
PATH
JITTER
ATTENUATOR
RX OR TX
PATH
MODE
LOOP 0..3
CLKE
RTIP
RRING
TTIP
TRING
JTAG
SERIAL/
PARALLEL
PORT
JASEL
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