參數(shù)資料
型號: LXT386
廠商: Intel Corp.
英文描述: QUAD T1/E1/J1 Transceiver
中文描述: 四T1/E1/J1收發(fā)器
文件頁數(shù): 63/78頁
文件大小: 500K
代理商: LXT386
QUAD T1/E1/J1 Transceiver
LXT386
Datasheet
63
Figure 22. Multiplexed Intel Read Timing
Table 47. Intel Mode Write Timing Characteristics
Parameter
2
Sym
Min
Typ
1
Max
Unit
Test Conditions
Address setup time to latch
Tsalw
10
ns
Valid address latch pulse width
Tvl
30
ns
Latch active to active write setup time
Tslw
10
ns
Chip select setup time to active write
Tscsw
0
ns
Chip select hold time from inactive write
Thcsw
0
ns
Address hold time from inactive ALE
Thalw
5
ns
Data valid to write active setup time
Tsdw
40
ns
Data hold time to active write
Thdw
30
ns
Address setup time to WR inactive
Thaw
2
ns
Address hold time from WR inactive
Tsaw
6
ns
1. Typical figures are at 25 C and are for design aid only; not guaranteed and not subject to production testing.
2. C
= 100pF on D0-D7, all other outputs are loaded with 50pF.
3. These times don
t apply for Reset Register 0Ah, since RDY line goes low once during the cycle. Please refer to Reset
Operation and Host Mode sections for more information.
ALE
RDY
Tristate
Tristate
ADDRESS
AD7-AD0
DATA OUT
tVL
tSLR
tSCSR
tVRD
tHSCR
tPRD
tZRD
tINT
tRDYZ
tVRDY
tDRDY
tDRDY
tSALR
tHALR
CS
RD
INT
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