參數(shù)資料
型號： LXT386
廠商： Intel Corp.
英文描述： QUAD T1/E1/J1 Transceiver
中文描述： 四T1/E1/J1收發(fā)器
文件頁數(shù)： 36/78頁
文件大?。?/td> 500K
代理商： LXT386
LXT386
—
QUAD T1/E1/J1 Transceiver
36
Datasheet
The R/W signal indicates the direction of the data transfer. The DS signal is the timing reference
for all data transfers and typically has a duty cycle of 50%. A read cycle is indicated by asserting R/
W High with a falling edge on DS. A write cycle is indicated by asserting R/W Low with a rising
edge on DS.
Both cycles require the CS signal to be Low and the Address pins to be actively driven by the
microprocessor. Note that CS and DS can be connected together in Motorola mode. In a write cycle
the data bus is driven by the microprocessor. In a read cycle the bus is driven by the LXT386.
3.12.2
Intel Interface
The Intel interface is selected by asserting the MOT/INTL pin High. The LXT386 supports non-
multiplexed interfaces with separate address and data pins when MUX is asserted Low, and
multiplexed interfaces when MUX is asserted High. The address is latched in on the falling edge of
ALE. In non-multiplexed mode, ALE should be pulled High. R/W is used as the RD signal and DS
is used as the WR signal. A read cycle is indicated to the LXT386 when the processor asserts RD
Low while the WR signal is held High. A write operation is indicated to the LXT386 by asserting
WR Low while the RD signal is held High. Both cycles require the CS signal to be Low.
3.13
Interrupt Handling
Interrupt Sources
There are three interrupt sources:
1. Status change in the Loss Of Signal (LOS) status register (04H). The LXT386
’
s analog/digital
loss of signal processor continuously monitors the receiver signal and updates the specific
LOS status bit to indicate presence or absence of a LOS condition.
2. Status change in the Driver Failure Monitoring (DFM) status register (05H). The LXT386
’
s
smart power driver circuit continuously monitors the output drivers signal and updates the
specific DFM status bit to indicate presence or absence of a secondary driver short circuit
condition.
3. Status change in the Alarm Indication Signal (AIS) status register (13H).The LXT386
’
s
receiver monitors the incoming data stream and updates the specific AIS status bit to indicate
presence or absence of a AIS condition.
3.13.1
Interrupt Enable
The LXT386 provides a latched interrupt output (INT). An interrupt occurs any time there is a
transition on any enabled bit in the status register. Registers 06H, 07H and 14H are the LOS, DFM
and AIS interrupt enable registers (respectively). Writing a logic
“
1
”
into the mask register will
enable the respective bit in the respective Interrupt status register to generate an interrupt. The
power-on default value is all zeroes. The setting of the interrupt enable bit does not affect the
operation of the status registers.
Registers 08H, 09H and 15H are the LOS, DFM and AIS (respectively) interrupt status registers.
When there is a transition on any enabled bit in a status register, the associated bit of the interrupt
status register is set and an interrupt is generated (if one is not already pending). When an interrupt
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