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參數(shù)資料
| 型號(hào)： | LXT386 |
| 廠(chǎng)商： | Intel Corp. |
| 英文描述： | QUAD T1/E1/J1 Transceiver |
| 中文描述： | 四T1/E1/J1收發(fā)器 |
| 文件頁(yè)數(shù)： | 41/78頁(yè) |
| 文件大?。?/td> | 500K |
| 代理商： | LXT386 |
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QUAD T1/E1/J1 Transceiver
—
LXT386
Datasheet
41
Table 16. LOS Interrupt Status Register, LIS (08H)
Bit
Name
Function
3-0
LIS3-LIS0
These bits are set to
“
1
”
every time a LOS status change has occurred since the last clear
interrupt in transceivers 3-0 respectively.
Table 17. DFM Interrupt Status Register, DIS (09H)
Bit
Name
Function
3-0
DIS3-DIS0
These bits are set to
“
1
”
every time a DFM status change has occurred since the last
cleared interrupt in transceivers 3-0 respectively.
Table 18. Software Reset Register, RES (0AH)
Bit
Name
Function
3-0
RES3-RES0
Writing to this register initiates a 1 microsecond reset cycle, except for Intel non-
multiplexed mode. When using Intel non-multiplexed host mode, extend cycle time to 2
microseconds. Please refer to Host Mode section for more information. This operation
sets all LXT386 registers to their default values.
Table 19. Performance Monitoring Register, MON (0BH)
Bit
Name
Function
3-0
A3:A0
Protected Monitoring selection. See
Table 1 on page 11
.
4-7
reserved
Reserved.
Table 20. Digital Loopback Register, DL (0CH)
Bit
1
Name
Function
2
3-0
DL3-DL0
Setting a bit to
“
1
”
enables digital loopback for the respective transceiver.
1. On power up all register bits are set to
“
0
”
.
2. During digital loopback LOS and TAOS stay active and independent of TCLK, while data received on TPOS/TNEG/TCKLK is
looped back to RPOS/RNEG/RCLK.
Table 21. LOS/AIS Criteria Register, LCS (0DH)
Bit
1
Name
Function
2
3-0
LCS3-LCS0
1
T1 Mode
2
Don
’
t care. T1.231 compliant LOS/AIS detection is used.
E1 Mode
Setting a bit to
“
1
”
selects the ETS1 300233 LOS. Setting a bit to
“
0
”
selects G.775 LOS
mode. AIS works correctly for both ETSI and ITU when the bit is cleared to
“
0
”
. See
errata revision 10.3 or higher for a way to implement ETSI LOS and AIS.
1. On power-on reset the register is set to
“
0
”
.
2. T1 or E1 operation mode is determined by the PSDR settings.
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