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參數(shù)資料
| 型號(hào)： | LXT386 |
| 廠商： | Intel Corp. |
| 英文描述： | QUAD T1/E1/J1 Transceiver |
| 中文描述： | 四T1/E1/J1收發(fā)器 |
| 文件頁數(shù)： | 19/78頁 |
| 文件大小： | 500K |
| 代理商： | LXT386 |
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QUAD T1/E1/J1 Transceiver
—
LXT386
Datasheet
19
J11
98
CS/
JASEL
DI
DI
Chip Select/Jitter Attenuator Select.
Host Mode
This active Low input is used to access the serial/parallel interface. For
each read or write operation, CS must transition from High to Low, and
remain Low.
Hardware Mode
This input determines the Jitter Attenuator position in the data path:
H12
1
MOT/INTL/
CODEN
DI
DI
Motorola/Intel/Codec Enable Select.
Host Mode:
When Low, the host interface is configured for Motorola microcontrollers.
When High, the host interface is configured for Intel microcontrollers.
Hardware Mode:
This pin determines the line encode/decode selection when in un-
ipolar mode:
When Low, B8ZS/HDB3 encoders/decoders are enabled for T1/E1
respectively. When High, enables AMI encoder/decoder (transparent
mode).
G13
76
AT2
AO
JTAG Analog Output Test Port 2.
H13
77
AT1
AI
JTAG Analog Input Test Port 1.
G12
72
TRST
JTAG Controller Reset.
Input is used to reset the JTAG controller. TRST
is pulled up internally and may be left disconnected.
F11
71
TMS
DI
JTAG Test Mode Select.
Used to control the test logic state machine.
Sampled on rising edge of TCK. TMS is pulled up internally and may be
left disconnected.
F14
69
TCK
DI
JTAG Clock.
Clock input for JTAG. Connect to GND when not used.
F13
73
TDO
DO
JTAG Data Output.
Test Data Output for JTAG. Used for reading all
serial configuration and test data from internal test logic. Updated on
falling edge of TCK.
F12
70
TDI
DI
JTAG Data Input
. Test Data input for JTAG. Used for loading serial
instructions and data into internal test logic. Sampled on rising edge of
TCK. TDI is pulled up internally and may be left disconnected.
E14
83
OE
DI
Output Driver Enable.
If this pin is asserted Low all analog driver outputs
immediately enter a high impedance mode to support redundancy
applications without external mechanical relays. All other internal circuitry
stays active. In software mode, TTIP and TRING can be tristated on a
port-by-port basis by writing a
‘
1
’
to the OEx bit in the Output Enable
Register (OER).
Table 1. Pin Assignments and Signal Descriptions
(Continued)
Ball #
PBGA
Pin #
LQFP
Symbol
I/O
1
Description
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
2. N/C means
“
Not Connected
”
JASEL
JA Position
L
Transmit path
H
Receive path
Z
Disabled
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