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參數(shù)資料
| 型號(hào)： | LXT386 |
| 廠商： | Intel Corp. |
| 英文描述： | QUAD T1/E1/J1 Transceiver |
| 中文描述： | 四T1/E1/J1收發(fā)器 |
| 文件頁數(shù)： | 20/78頁 |
| 文件大小： | 500K |
| 代理商： | LXT386 |
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LXT386
—
QUAD T1/E1/J1 Transceiver
20
Datasheet
E13
84
CLKE
DI
Clock Edge Select.
In clock recovery mode, setting CLKE High causes
RDATA or RPOS and RNEG to be valid on the falling edge of RCLK and
SDO to be valid on the rising edge of SCLK. Setting CLKE Low makes
RDATA or RPOS and RNEG to be valid on the rising edge of RCLK and
SDO to be valid on the falling edge of SCLK. In Data recovery Mode,
RDATA or RPOS/RNEG are active High output polarity when CLKE is
High and active low polarity when CLKE is Low.
N/C
2
100
RESET
DI
Reset Input.
(Added in Revision B1) In either hardware mode or software
mode, setting RESET low will begin to initialize the LXT386 and freeze the
device until set high. One microsecond after setting RESET high,
initialization will complete and the LXT386 will be ready for normal
operation. For Revision B1 only, the device requires a pull up resistor to
VCC at this pin between 1 and 10 kohms in value. It is not necessary to
retain the pull up resistor for any other revision. Please refer to the section
on Reset Operation for more information. The BGA package does not
have this pin feature.
A6, A9
B: 1, 2, 3, 6,
9, 12, 13, 14
C6, C9
D: 1, 2, 3, 6,
9, 12, 13, 14
G4, G11
H4, H11
5, 7, 10,
11, 65, 66,
74
GND
S
Power Supply Ground.
Connect all pins to power supply ground.
Table 1. Pin Assignments and Signal Descriptions
(Continued)
Ball #
PBGA
Pin #
LQFP
Symbol
I/O
1
Description
1. DI: Digital Input; DO: Digital Output; DI/O: Digital Bidirectional Port; AI: Analog Input; AO: Analog Output S: Power Supply;
N.C.: Not Connected.
2. N/C means
“
Not Connected
”
CLKE RPOS/RNEG SDO
Low
High
SCLK
SCLK
RCLK
RCLK
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