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參數(shù)資料
| 型號(hào)： | LXT386 |
| 廠商： | Intel Corp. |
| 英文描述： | QUAD T1/E1/J1 Transceiver |
| 中文描述： | 四T1/E1/J1收發(fā)器 |
| 文件頁數(shù)： | 37/78頁 |
| 文件大小： | 500K |
| 代理商： | LXT386 |
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QUAD T1/E1/J1 Transceiver
—
LXT386
Datasheet
37
occurs, the INT pin is asserted Low. The output stage of the INT pin consists only of a pull-down
device; an external pull-up resistor of approximately 10k ohm is required to support wired-OR
operation.
3.13.2
Interrupt Clear
When an interrupt occurs, the interrupt service routine (ISR) should read the
interrupt status
registers
(08H, 09H and 15H) to identify the interrupt source. Reading the Interrupt Status register
clears the
“
sticky
”
bit set by the interrupt. Automatically clearing the register prepares it for the
next interrupt.
The ISR should then read the corresponding
status monitor register
to obtain the current status of
the device. Note that there are three status monitor registers: the LOS (04H), the DFM (05H) and
the AIS (013H). Reading either status monitors register will clear its corresponding interrupts on
the rising edge of the read or data strobe. When all pending interrupts are cleared, the INT pin goes
High.
3.14
Serial Host Mode
The LXT386 operates in Serial Host Mode when the MODE pin is tied to VCC
÷
2.
Figure 14
shows
the SIO data structure. The registers are accessible through a 16 bit word: an 8bit Command/
Address byte (bits R/W and A1-A7) and a subsequent 8bit data byte (bits D0-7). Bit R/W
determines whether a read or a write operation occurs. Bits A5-0 in the Command/Address byte
address specific registers (the address decoder ignores bits A7-6). The data byte depends on both
the value of bit R/W and the address of the register as set in the Command/Address byte.
Figure 14. Serial Host Mode Timing
CS
SCLK
ADDRESS/COMMAND BYTE
INPUT DATA BYTE
R/W
A1
A2
A3
A4
A5
A6
X
A7
X
D0
D1
D2
D3
D4
D5
D6
D7
SDI
SDO - REMAINS HIGH Z
R/W
= 1: Read from the LXT386
R/W
= 0: Write to the LXT386
X
= Don
’
t care
SDO IS DRIVEN IF R/W = 1
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