參數(shù)資料
型號: LXT386
廠商: Intel Corp.
英文描述: QUAD T1/E1/J1 Transceiver
中文描述: 四T1/E1/J1收發(fā)器
文件頁數(shù): 44/78頁
文件大?。?/td> 500K
代理商: LXT386
LXT386
QUAD T1/E1/J1 Transceiver
44
Datasheet
Table 28. AIS Interrupt Enable Register, AISIE (14H)
Bit
1
Name
Function
3-0
AISIE3-AISIE0
Transceiver 3-0 AIS interrupts are enabled by writing a
1
to the respective bit.
7-4
-
Write
0
to these positions for normal operation.
1. On power-up all the register bits are set to
0
.
Table 29. AIS Interrupt Status Register, AISIS (15H)
Bit
1
Name
Function
3-0
AISIS3-AISIS0
These bits are set to
1
every time a AIS status change has occurred since the last clear
interrupt in transceivers 3-0 respectively.
1. On power-up all the register bits are set to
0
.
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