參數(shù)資料
型號(hào)： LXT386
廠商： Intel Corp.
英文描述： QUAD T1/E1/J1 Transceiver
中文描述： 四T1/E1/J1收發(fā)器
文件頁數(shù)： 35/78頁
文件大?。?/td> 500K
代理商： LXT386
QUAD T1/E1/J1 Transceiver
—
LXT386
Datasheet
35
3.11
Interfacing with 5V logic
The LXT386 can interface directly with 5V logic. The internal input pads are tolerant to 5V outputs
from TTL and CMOS family devices.
3.12
Parallel Host Interface
The LXT386 incorporates a highly flexible 8-bit parallel microprocessor interface. The interface is
generic and is designed to support both non-multiplexed and multiplexed address/data bus systems
for Motorola and Intel bus topologies. Two pins (MUX and MOT/INTL) select four different
operating modes as shown in
Table 5
.
The interface includes an address bus (A4 - A0) and a data bus (D7 - D0) for non-multiplexed
operation and an 8-bit address/data bus for multiplexed operation. WR, RD, R/W, CS, ALE, DS,
INT and RDY/ACK are used as control signals. A significant enhancement is an internal wait-state
generator that controls an Intel and Motorola compatible handshake output signal (RDY/ACK). In
Motorola mode ACK Low signals valid information is on the data bus. During a write cycle a Low
signal acknowledges the acceptance of the write data.
In Intel mode RDY High signals to the controlling processor that the bus cycle can be completed.
While Low the microprocessor must insert wait states. This allows the LXT386 to interface with
wait-state capable micro controllers, independent of the processor bus speed. To activate this
function a reference clock is required on the MCLK pin.
There is one exception to write cycle timing for Intel non-multiplexed mode: Register 0Ah, the
reset register. Because of timing issues, the RDY line remains high after the first part of the cycle
is done, not signalling write cycle completion with another transition low. In this mode, add 2
microseconds of delay, overall 3 microseconds from CS low to end of cycle, to allow the reset
cycle to completely initialize the device before proceeding.
An additional active Low interrupt output signal indicates alarm conditions like LOS and DFM to
the microprocessor.
The LXT386 has a 5 bit address bus and provides 18 user accessible 8-bit registers for
configuration, alarm monitoring and control of the chip.
3.12.1
Motorola Interface
The Motorola interface is selected by asserting the MOT/INTL pin Low. In non-multiplexed mode
the falling edge of DS is used to latch the address information on the address bus. In multiplexed
operation the address on the multiplexed address data bus is latched into the device with the falling
edge of AS. In non-multiplexed mode, AS should be pulled High.
Table 5. Microprocessor Parallel Interface Selection
MUX
MOT/INTL
Operating Mode
Low
Low
Motorola Non-Multiplexed
Low
High
Intel Non-Multiplexed
High
Low
Motorola Multiplexed
High
High
Intel Multiplexed
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