參數(shù)資料
型號： LXT386
廠商： Intel Corp.
英文描述： QUAD T1/E1/J1 Transceiver
中文描述： 四T1/E1/J1收發(fā)器
文件頁數(shù)： 46/78頁
文件大小： 500K
代理商： LXT386
LXT386
—
QUAD T1/E1/J1 Transceiver
46
Datasheet
Table 30. TAP State Description
State
Description
Test Logic Reset
In this state the test logic is disabled. The device is set to normal operation mode. While in this state, the
instruction register is set to the ICODE instruction.
Run -Test/Idle
The TAP controller stays in this state as long as TMS is low. Used to perform tests.
Capture - DR
The Boundary Scan Data Register (BSR) is loaded with input pin data.
Shift - DR
Shifts the selected test data registers by one stage tword its serial output.
Update - DR
Data is latched into the parallel output of the BSR when selected.
Capture - IR
Used to load the instruction register with a fixed instruction.
Shift - IR
Shifts the instruction register by one stage.
Update - IR
Loads a new instruction into the instruction register.
Pause - IR
Pause - DR
Momentarily pauses shifting of data through the data/instruction registers.
Exit1 - IR
Exit1 - DR
Exit2 - IR
Exit2 - DR
Temporary states that can be used to terminate the scanning process.
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