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參數(shù)資料
| 型號： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 115/162頁 |
| 文件大?。?/td> | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
118
PM2329 ClassiPI Network Classification Processor Datasheet
4.2.2.19 Channel Status Register (CSR; Base 0 +00h)
Channel Register
Access Mode: Read Only, Global
This register indicates the status of the corresponding channel. In single-channel mode, only CSR0 is valid.
Since this is a Channel Register, each channel has a corresponding Channel Status register when the
PM2329 is in the multi-channel mode. When channels are concatenated, the status for the concatenated
channel are all available by reading the Channel Status register corresponding to the lowest numbered
concatenated channel. Reading a Channel Status register corresponding to an unassigned channel in the
Channel Assignment Register will return invalid value.
Channel Result FIFO Full
This bit is set when the result FIFO of the corresponding channel becomes full. If this condition is not
serviced by the processor, the internal processing engine will eventually stall since any results that are
generated can not be transferred to the Result FIFO.
Channel OC Sequence Halted
This bit is set when the PM2329 has completed the current OC processing for the corresponding channel
and...
1.
OC Trace Enable bit is 0 and OC Sequence Mode bit is 1 (Processor controlled OC sequencing), or
2.
OC Trace Enable bit is 1 and OC Sequence Mode bit is 0 (automated OC sequencing with Trace)
The OC Sequnce Halt State bit indicates the reason for the halt condition.
Channel OC Sequence Halt Condition
If the OC Sequence Halted bit is 0 then this bit is a don
’
t care.
If the OC Sequence Halted bit is 1 and this bit is 0, the PM2329 has reached a break condition for the
corresponding channel--it has completed execution of the previous OC and this just completed OC was
not the last OC in the specified sequence.
Bit
Range
63:8
7
6
5
Size
56
1
1
1
Name
Value after
Reset
Undefined
0
0
Undefined
(Reserved)
Channel Result FIFO Full
Channel OC Sequence Halted
Channel OC Sequence Halt
Condition
(Reserved)
Channel Packet Buffer Available
Channel Result Available
Channel OC Sequence
Terminated
(Reserved)
4
3
2
1
1
1
1
1
Undefined
1
0
0
0
1
Undefined
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