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參數(shù)資料
| 型號(hào)： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 69/162頁 |
| 文件大小： | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
72
PM2329 ClassiPI Network Classification Processor Datasheet
When the Global address space is accessed (SA[15] is high), all PM2329 devices participate in the
operation. When a Global Write is performed, all PM2329 devices are written. When a Global Read is
performed, all devices in the cascade respond in turn, while an internal address resolution mechanism
within the PM2329 devices avoids contention.
Once initialization is complete and local PM2329 registers are configured, the network processor
thereafter treats the bank of cascaded PM2329 devices as a single PM2329 device; whether a single device
or a cascade of devices is implemented, there is no difference in the interface protocol. (Thus, in discussion
throughout this data book, references to
“
the PM2329 device
”
can mean a single device or multiple
cascaded devices.)
4.1.2 Channels
The PM2329 implements a set of thirty two channels to support independent contexts of the external
network processor (a network processor divides packets among its various processing cores; each stream
of packets from any given core represents a context to the PM2329 device[s]). PM2329 channels can be
assigned to these contexts; each context can send a packet to PM2329 in an independent manner and then
fetch its own classification results. Packet input activities, as well as access to results, can be interleaved
between the various contexts.
To facilitate packet transfers, on board each PM2329 device is a Packet Input Buffer--an input FIFO which
is the first element in the data path inboard from the network processor (system) interface. The Packet
Input Buffer
’
s physical size is 256 bytes times the maximum number of channels supported in hardware, or
256 x 32 bytes. The Packet Input Buffer can be accessed using either a single write port (called the Packet
Buffer Input Register, or PBIR), or with SRAM-like addressing.
The Packet Input Buffer resides in Global address space. Thus, when packets are written to a Packet Input
Buffer, they are written simultaneously to all Packet Input Buffers of all cascaded PM2329 devices. At any
given time, then, all Packet Input Buffers are identical, and all PM2329 devices in the cascade have the
opportunity to utilize or classify each packet.
Figure 23 PM2329 Packet Input Buffer
To facilitate the return of processing information back to the network processor
’
s context, each PM2329
device has a Results FIFO that can hold 8 entries per channel, or (32 x 8) = 256 entries total. Like the
Packet Input Buffer, the Results FIFO can be accessed using either a single write port, or with SRAM-like
addressing. The Results FIFO also resides in Global address space.
256 bytes
seg32
(one per
channel)
8K Byestoa
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