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Document ID: PMC-2010146, Issue 4
126
PM2329 ClassiPI Network Classification Processor Datasheet
Note that the Data Results FIFO returns values associated with depth level 0 only. Words at other levels, if
defined, must be accessed using E-RAM indirect addressing mechanism.
(The only exception is in case of a single device connected to a single external E-RAM memory device
with both ECD and EDD buses connected to the same physical memory device. In this case, D-Word 0 at
the next sequential address is accessed and returned in the Data Results FIFO.)
4.3 Indirectly Addressable Locations
This section describes indirectly addressable locations in the PM2329 and in the E-RAM, which fall in one
of the following two classes:
Rule Memory Cells
E-Words
4.3.1 Rule Memory Cells
Indirect Access using: Rule Indirect Registers
Access Mode:
Local
Rule Memory Cells are accessed by indirect addressing using the Rule Indirect Address, Command and
Data Register Set. The Rule Memory Cells store the Rule Data and the Rule Control fields used when an
OC is executed. The Rule Memory Cells are 136 bits in size.
The format of the Rule Memory Cells is same as the Rule Indirect Data Register Set.
Detailed rule operation is described in Chapter 5.
Table 27
Data Results FIFO Ouput Register (32-bit mode)
Register Name
Size
32
Responding
Device
CID 0
Address
Base 1 + 08h
Data Result FIFO Output Register 0
(DW0)
Data Result FIFO Output Register 1
(DW1)
Data Result FIFO Output Register 2
(DW2)
Data Result FIFO Output Register 3
(DW3)
Data Result FIFO Output Register 4
(DW4)
Data Result FIFO Output Register 5
(DW5)
Data Result FIFO Output Register 6
(DW6)
32
CID 1
Base 1 + 0Ch
32
CID 2
Base 2 + 08h
32
CID 3
Base 2 + 0Ch
32
CID 4
Base 2 + 10h
32
CID 5
Base 2 + 14h
32
CID 6
Base 2 + 18h