參數(shù)資料
型號: PM2329
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 92/162頁
文件大?。?/td> 1581K
代理商: PM2329
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
Internal Use
Document ID: PMC-2010146, Issue 4
95
PM2329 ClassiPI Network Classification Processor Datasheet
Trigger
This field specifies which of the (up to) eight 32-bit data words will serve as the Trigger for the PM2329
to perform the read or write operation to the E-RAM. After the Trigger word is written to or read from,
the device performs Read or Write operation on the E-RAM. These bits are programmed as follows:
000
E-RAM Indirect Data Register 0 or C-Word Bus
001
E-RAM Indirect Data Register 1 or D-Word 0 Bus
010
E-RAM Indirect Data Register 2 or D-Word 1 Bus
011
E-RAM Indirect Data Register 3 or D-Word 2 Bus
100
E-RAM Indirect Data Register 4 or D-Word 3 Bus
101
E-RAM Indirect Data Register 5 or D-Word 4 Bus
110
E-RAM Indirect Data Register 6 or D-Word 5 Bus
111
E-RAM Indirect Data Register 7 or D-Word 6 Bus
Register Set Ready
This bit when
1
indicates that the E-RAM Indirect registers are currently not in use. It gets cleared
when a read or write command is issued and remains
0
as long as the device is busy performing this
operation. It is set again as soon as the device has executed the read or write operation to the E-RAM.
For correct operation, the processor must check that this bit is set before it writes to the EICR, EIAR or
EIDR. When the RSR bit is 0, write cycles to any of these (RICR, RIAR or RIDR) registers are ignored.
This is a read-only bit and is set to
1
after reset.
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