參數(shù)資料
型號: PM2329
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 9/162頁
文件大?。?/td> 1581K
代理商: PM2329
PM2329 ClassiPI Network Classification Processor Datasheet
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
Internal Use
Document ID: PMC-2010146, Issue 4
12
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 33
Table 34
Table 35
Table 36
Table 37
Table 38
Table 39
Table 40
Timing and Common Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
System Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ERAM Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Cascade Interface Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Test Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
VDD and VSS Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Signals Listed by Ball Assignment; Rows A through C . . . . . . . . . . . . . . . . 33
Signals listed by Ball Assignment; Rows D through K . . . . . . . . . . . . . . . . . 34
Signals listed by Ball Assignment; Rows L through W . . . . . . . . . . . . . . . . . 35
Signals listed by Ball Assignment; Rows Y through AD . . . . . . . . . . . . . . . . 36
Signals listed by Ball Assignment; Rows AE and AF . . . . . . . . . . . . . . . . . . 37
Signals Listed by Name (Alphabetically) . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
PSPBA Deassertion Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
System Bus 64-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
System Bus 32-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Cascade Size vs. Maximum Physical E-RAM Width . . . . . . . . . . . . . . . . . . 54
PM2329 Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Channel Register Block Base Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Channel Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
E-Word Depth Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
EMA[18:17] Usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Direction Specifier Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
OC Conductor Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Processor Controlled OC Sequencing & Trace OC Execution . . . . . . . . . . 109
Timestamp Increment Interval Example (SCLK 66.67 MHz) . . . . . . . . . . . 111
Data Results FIFO Output Register (64-bit mode) . . . . . . . . . . . . . . . . . . . 125
Data Results FIFO Ouput Register (32-bit mode) . . . . . . . . . . . . . . . . . . . 126
Common Control Rule - CCR Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Operations Supported for Rule Data Sub-fields . . . . . . . . . . . . . . . . . . . . . 138
Masked sub-field and Associated Mask Source . . . . . . . . . . . . . . . . . . . . . 139
OCC Sequencing Control Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
OCC Sequencing Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Registers Applicable to OCC Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . 142
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Terminal Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
System Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
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