參數(shù)資料
型號: PM2329
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 29/162頁
文件大?。?/td> 1581K
代理商: PM2329
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
Internal Use
Document ID: PMC-2010146, Issue 4
32
PM2329 ClassiPI Network Classification Processor Datasheet
Table 6
VDD and VSS Signals
Signal Name
AVSS1
AVSS2
Ball #
M1
R1
Size
Description
2
PLL analog ground
Each AVSS signal should be tied to its corresponding
AVDD signal using two low-inductance bypass
capacitors (1-10 uF and 0.01-0.001uF). These signals
should not be tied to the general ground plane. In order
to ensure that the digital and analog sections of the on-
chip PLLs have a common reference, they are tied to a
ground reference internally on-chip.
PLL analog power 1.5V
AVDD1
AVDD2
N1
P1
2
All signals must be connected to an appropriate power
supply for correct device operation.
Core ground
CVSS
Refer to
section
2.3 tables
2.3-2.7
Refer to
section
2.3 tables
2.3-2.7
Refer to
section
2.3 tables
2.3-2.7
Refer to
section
2.3 tables
2.3-2.7
16
All signals must be connected to an appropriate ground
plane for correct device operation.
Core power 1.5V
CVDD
16
All signals must be connected to an appropriate power
supply for correct device operation.
I/O ground
VSS
64
All signals must be connected to an appropriate ground
plane for correct device operation.
I/O power 3.3V
VDD
16
All signals must be connected to an appropriate power
supply for correct device operation.
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