Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
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Document ID: PMC-2010146, Issue 4
19
PM2329 ClassiPI Network Classification Processor Datasheet
1.4.6.1 Operation Cycles, Descriptors and E-RAM
The Operation Control Logic controls the execution of the operation cycles. An OC is the atomic action of
looking up a packet against a class of rules and returning a match index. In order to run an Operation
Cycle, the rules that will participate in the OC must be specified. This information is provided by using an
Operation Cycle Descriptor (OCD). Each descriptor stores adequate information to describe the start and
end of a rule partition. Rule partitions can be uniquely described in each cascaded PM2329 device. The
OCDs are arranged in the form of a table within each device, and are specified by an index into this table.
In the minimal mode, a standalone PM2329 device can execute a sequence of up to 4 fixed operation
cycles.
To support enhanced functionality including conditional sequencing and user data storage, the PM2329
supports an external synchronous SRAM (E-RAM) that contains control and data information. The control
information is stored in Control Words (C-Words). The Operation Control Logic can execute operation
cycles based on a flow control mechanism driven by these C-Words stored in the external SRAM. Each
control word contains an index into the OC Descriptor Table and identifies a single OC Descriptor. Control
words also supply control information that drives the Policy Search Engine. Control words can also specify
branch conditions that can start the execution of another OC based on the result of the current OC. Besides
C-Words, the E-RAM also contains Data Words (D-Words). These D-Words contain statistical and state
information such as Packet Count, Byte Count, TCP State and Time-Stamp. D-Words are typically
accessed and updated by the device after a match or when an OC execution is complete.
1.5 System Diagram
Figure 1 illustrates one possible application of the PM2329 in a line interface card of a high performance
switch.
Figure 1 System Block Diagram
PACKET DATA
Port Interface
Control
Processor
Switch
Matrix
OR
Backplane
ClassiPI
1 - 8 Chips
SRAM
User Data +
Sequence Control
(E-RAM)
PHYSICAL
P
R