Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
99
PM2329 ClassiPI Network Classification Processor Datasheet
4.2.2.10 Interrupt Enable Register (IER; 8238h)
Access Mode: Read/Write, Global
This register specifies the mask bits for the various conditions that can cause the PM2329 to assert an
external interrupt. If a bit is set, an occurrence of the corresponding condition causes the interrupt signal to
be asserted. The OCST status bit is always cleared on reading the STSR. The interrupt signal will continue
to be asserted until either the interrupting condition is removed, or the corresponding enable bit in this
register is reset.
The bits in this register are defined below.
Enable Result FIFO Full Interrupt (RFOF)
If this bit is set, an interrupt is generated when a result FIFO is full.
Enable OC Sequence Halted Interrupt (OCSH)
If this bit is set, an interrupt is generated when the OC Sequence is halted due to a
“
Break
”
or
“
Wait
”
condition (see Status register for definitions of these conditions). OC Sequence Halted (Status register
bit 5) will be set when this interrupt is asserted.
Enable Idle Interrupt (IDLE)
If this bit is set, an interrupt is generated when all Packet Buffers are empty and all result FIFOs are
empty.
Table 21
EMA[18:17] Usage
Depth
EMA[18]
EMA[17]
1
2
4
NC
NC
Connected
NC
Connected
Connected
Bit
Range
63:8
7
6
5
Size
56
1
1
1
Name
Value after
Reset
Undefined
0
Undefined
0
(Reserved)
Enable Result FIFO Full Interrupt (RFOF)
(Reserved)
Enable OC Sequence Halted Interrupt
(OCSH)
Enable Idle Interrupt (IDLE)
Enable Packet Buffer Available Interrupt
(PBA)
Enable Result Available Interrupt (RAV)
Enable OC Sequence Terminated Interrupt
(OCST)
Interrupt Enable
4
3
1
1
0
0
2
1
1
1
0
0
0
1
0