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參數(shù)資料
| 型號(hào)： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 80/162頁 |
| 文件大?。?/td> | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
83
PM2329 ClassiPI Network Classification Processor Datasheet
(bit 8) is for Rule Indirect Data 4. For example, programming a value of 01100 will enable writes to
words 1 and 2 only. During read, only the enabled words are read.
For a detailed description of the Rule Memory read and write operation, refer to the Rule Indirect Data
Register set description.
Auto-Increment
If this bit is
‘
1
’
, then after the read or write operation to the Rule Memory, the Rule Indirect Address
Register is automatically incremented to point to the next cell (post-increment). This bit will normally
be written with
’
1
’
when a block of data needs to be transferred to or from the Rule Memory.
If this bit is
‘
0
’
, the Rule Indirect Address Register is unchanged after a read or write operation to the
Rule Memory.
Trigger
These bits specify which of the five 32-bit data words will serve as the Trigger for the PM2329 to
perform the internal read or write operation to the Rule Memory. After the Trigger word is written to or
read from, the device performs Read or Write operation on the rule memory. These bits are programmed
as follows:
000
Rule Indirect Data Register 0
001
Rule Indirect Data Register 1
010
Rule Indirect Data Register 2
011
Rule Indirect Data Register 3
100
Rule Indirect Data Register 4
101
(Reserved)
110
(Reserved)
111
(Reserved)
Register Set Ready
This bit when
’
1
’
indicates that the Rule Indirect registers are currently not in use. It is cleared when a
read or write command is issued and remains
’
0
’
as long as the device is busy performing this operation.
It is set when the device has internally executed the read or write operation. For correct operation, the
processor must check that this bit is set before it writes to the RICR, RIAR or RIDR. When the RSR bit
is 0, write cycles to any of these (RICR, RIAR or RIDR) registers are ignored. This is a read-only bit
and is set to
‘
1
’
after reset.
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