Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
87
PM2329 ClassiPI Network Classification Processor Datasheet
Read and write sequences are explained in greater detail below.
For random read operation, the processor must perform the following steps.
1.
Check the RSR bit is set to
‘
1
’
to ensure the previous memory transaction is complete.
2.
Set up RICR with the Data Enable and Trigger fields, and the auto-increment bit reset to
‘
0
’
.
3.
Set up the RIAR with the address of the location to be read.
4.
Read the trigger word and discard the value read back.
5.
Wait for RSR bit to be set to
‘
1
’
6.
Read the content of the addressed location by reading the RIDR (the RIDR set as trigger word should be
read last).
To read a set of random locations, steps 1 through 6 outlined above can be repeated. However, a set of
random reads can be optimized (only one dummy read for a set of random reads), if (step 5a) the address of
the next random location to be read is loaded in the RIAR after step 5, before reading the previous
locations content in step 6. In this case, the processor can simply repeat steps 5, 5a, and 6 until all the
ramdom location have been accessed.
For random write operation, the processor must perform the following steps.
1.
Check the RSR bit is set to
‘
1
’
to ensure the previous memory transaction is complete.
2.
Set up RICR with the Data Enable and Trigger fields, and the auto-increment bit reset to
‘
0
’
.
3.
Set up the RIAR with the address of the location to be written.
4.
Write the RIDR, the trigger word should be written last.
For sequential read operation, the processor must perform the following steps.
1.
Check the RSR bit is set to
‘
1
’
to ensure the previous memory transaction is complete.
2.
Set up RICR with the Data Enable and Trigger fields, and the auto-increment bit set to
‘
1
’
.
3.
Set up the RIAR with the start address of the locations to be read.
4.
Read the trigger word and discard the value read back.
5.
Wait for RSR bit to be set to
‘
1
’
6.
Read the content of the addressed location by reading the RIDR (the trigger word should be read last).
Repeat steps 5 and 6 to read the rest of the memory block.