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參數(shù)資料
| 型號(hào)： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 98/162頁(yè) |
| 文件大?。?/td> | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
101
PM2329 ClassiPI Network Classification Processor Datasheet
Bit definitions for this register are as follows:
Result FIFO Full
This bit is set when any one of the result FIFOs becomes full. If this condition is not serviced by the
processor, the internal processing engine will eventually stall since any results that are generated can not
be transferred to the Result FIFO.
The OC Processing Halt State bit indicates the reason for the halt condition.
OC Sequence Halt Condition
If the OC Sequence Halted bit (bit 5) is 0, then this bit is a don
’
t care.
If the OC Sequence Halted bit is 1, and this bit is 0, the PM2329 has reached a
“
Break
”
condition--it has
completed execution of the previous OC, and that previous OC was not the last OC in the specified
sequence.
If the OC Sequence Halted bit is 1, and this bit is 1, the PM2329 has reached a
“
Wait
”
condition--it has
completed execution of the previous OC, and that previous OC was the last OC in the specified
sequence.
OC Sequence Halted
This bit is set when the PM2329 is halted awaiting a command from the network processor, and either:
1.
OC Trace Enable bit is 0 and OC Sequence Mode bit is 1 (Processor controlled OC sequencing), or
2.
OC Trace Enable bit is 1 and OC Sequence Mode bit is 0 (automated OC sequencing with Trace).
The OC Sequence Halt Condition bit (bit 6) indicates the reason for the halt condition.
If the processor writes to the AOCCR register, this bit is reset.
Idle
This bit is set when all Packet Buffers are empty and all result FIFOs are empty. When this bit is set, the
PM2329 is in Idle condition and the PM2329 operating modes can be reprogrammed without losing
coherency.
This bit is cleared when any of the Packet Buffers is written to or at least one result is present in the
result FIFO. If the PM2329 operating modes are reprogrammed when this bit is clear, data or results can
be lost.
Packet Buffer Available
This bit when set indicates that the PM2329 is ready to receive another packet into one or more of the
Packet Buffers. When the PM2329 is operating in multi-channel mode, this bit when set indicates that at
least one of the Packet Buffers is available. The Channel Packet Buffer Available bit in the Channel
Status Registers can be used to determine channel(s) for which the Packet Buffer(s) are available. For
further information about Packet Buffer Available status, see the Channel Status Register description.
This bit is cleared when all the individual Channel Packet Buffer Available bits are clear.
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