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| 型號(hào)： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 24/162頁(yè) |
| 文件大小： | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
27
PM2329 ClassiPI Network Classification Processor Datasheet
SOE*
U3
1
I
System Output Enable (Active Low)
This signal is driven active low by the Packet Processor
to enable PM2329 data onto the external bus when a
read operation is performed. This signal must be held
high during write cycle.
System Write Enable (Active Low)
SRW*
V2
1
I
If SyncBurst mode is selected, this signal can be tied
permanently low.
If ZBT mode is selected, this signal should be driven
low during a write cycle and held high during a read
cycle.
System Write High Enable (Active Low)
or System Address bit 2
SWHE* {SA[2]}
U4
1
I
In 64-bit mode, this signal is SWHE* and should be
asserted during write cycles to indicate write data
transfers on the upper 32 bits of the System Data Bus
(SD[63:32]).
In 32-bit mode, this signal is connected to the System
Address line #2 of the Packet Processor, and functions
as the SA[2] signal.
System Write Low Enable (Active Low)
SWLE* {SWE*}
W1
1
I
In 64-bit mode, this signal should be asserted during
write cycles to indicate write data transfers on the lower
32 bits of the System Data Bus (SD[31:0]).
In 32-bit mode, this signal should be asserted during
write cycle.
Packet Source Packet Direction
PSPD
E24
1
I
This signal can be used by the PS to indicate the
direction of packet movement (upstream/downstream)
to the PM2329. This signal should indicate the packet
direction during each cycle of packet data transfer after
PSPBA has been asserted. This signal is used in DMA
mode only and should be tied low otherwise.
Packet Source End of Packet
PSEOP
E26
1
I
PS asserts this signal to indicate that the current
packet transfer to the PM2329 is complete. The
PM2329 can now process the completed packet. This
signal is typically connected to the Terminal Count pin
of the DMA device.
This signal is used in DMA mode only and should be
tied low otherwise.
Table 2
System Interface Signals
Signal Name
Ball #
Size
I/O
Description
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