參數(shù)資料
型號: PM2329
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數(shù): 140/162頁
文件大小: 1581K
代理商: PM2329
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
Internal Use
Document ID: PMC-2010146, Issue 4
143
PM2329 ClassiPI Network Classification Processor Datasheet
5.3.2.1 Trace Feature
OC Trace Enable can be set to debug the OC processing regardless of the OC Sequencing employed
(Automated or Processor Controlled). With the OC Trace Enable bit set, the PM2329 will enter a Halt state
at the end of each OC execution. The Status register will indicate the Halted state and the Halt condition
(Break or Wait). The processor can examine the state of the device between OC execution by reading
various registers, rule memory or ERAM memory locations. The OC execution can be terminated or
continued, as explained below.
Note that processor intervention is required if the Trace feature is enabled, regardless of the OC Seqencing
Mode employed.
When the PM2329 enters the Halt condition (Break or Wait), the processor can use the AOCC register to
determine how the OC processing is to continue. The operations and conditions for their employ are listed
below.
1.
Terminate Sequence
When a Break or Wait condition occurs, the processor can write an EPP word to the AOCC register.
This terminates the current packet processing, and packet is discarded.
2.
Continue Sequence
When a Break condition (end of OC execution) occurs, the processor can issue a Continue Sequence
command by writing a non-EPP word to the AOCC register. This causes the PM2329 to continue
processing the current packet with the next specified OC.
3.
Start New Sequence
When a wait condition (end of OC sequence) occurs, the processor can Start New Sequence by writing a
non-EPP, OCC format-compatible word to the AOCC register.
Figure 30
shows the Halt state (Break or Wait) entered by the PM2329 as the OC execution proceeds with
the Trace feature enabled.
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