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| 型號(hào)： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁(yè)數(shù)： | 55/162頁(yè) |
| 文件大?。?/td> | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
58
PM2329 ClassiPI Network Classification Processor Datasheet
3.1.1 Basic Blocks
As illustrated in
Figure 15
, the PM2329 consists of 7 major internal blocks:
1. System Interface
This block allows access to the PM2329 registers, and implements specific registers for programming
the Rule Memory, transferring packet data to the PM2329, and reading Results. Additionally, indirect
memory access registers in this block provide access to the E-RAM memory.
2. Field Extraction Engine (FEE)
This block includes the 8 KB Packet Input Buffer which can store multiple packets in the single channel
mode or one for each channel, in the multi channel mode. This block performs data extraction on the
packet and transfers this data to the Policy Search Engine for classification. The extracted data can be
either from the header or pattern data from the user data field.
3. Control Logic
This block controls the overall operation of the device.
4. Policy Search Engine (PSE)
This is the core of the PM2329 classification engine and holds the policy database (also known as the
Rule Memory). This block executes Operation Cycles (OCs) and returns results.
5. Results FIFO
This block contains the Results FIFO logic. The results of packet processing are stored in the Results
FIFO. In multi-channel mode, results are organized on a per channel basis in the FIFO.
6. E-RAM Interface
This block interfaces with the External RAM (E-RAM), both Control RAM and Data RAM. The E-
RAM is useful for conditional sequencing of OCs and for maintaining statistics and user data.
7. Cascade Logic
This block provides the interface between multiple PM2329 devices in a cascade configuration. It
resolves priorities between devices and enables processing across the cascade.
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