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參數(shù)資料
| 型號： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 70/162頁 |
| 文件大?。?/td> | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
73
PM2329 ClassiPI Network Classification Processor Datasheet
The PM2329 channels are implemented through segmentation of the Packet Buffer and the Results FIFO.
Channel segments may be concatenated to allow larger packet or result storage for a given channel (with
correspontingly fewer channels supported).
4.1.3 Channel Register Blocks
PM2329 registers involved in packet transfer, packet processing status and packet results are organized
into Channel Register blocks. There is one block of Channel registers for each of the 32 possible channels.
These registers reside in Global address space. Thus, every PM2329 in a cascade has them, and a write to
them by the network processor affects all devices in the cascade.
Figure 24 Channel Register Blocks
As illustrated in Figure 24, each channel
’
s register block is spread over four address regions identified by
base addresses 0 to 3. However, the specific registers of each channel have a unique offset relative to base
addresses. That is, for any given channel, the offset distinguishes the channel
’
s registers from
corresponding registers of other channels. Thus, each context on the packet processor can access a
particular channel easily, and perform its own packet processing independently. (The four base address
spaces differ in size, so a channel
’
s offset from Base 0 will differ from its offset from Base 1, or 2, or 3.)
Figure 25 and Table 18 show the complete Register Block address space.
4.1.4 Direct and Indirect Access
The registers of the PM2329 are accessed using direct addressing by directly reading or writing to these
registers. Memory locations controlled by the PM2329 (the E-RAM and PM2329 Rule Memory), however,
are accessed using Indirect Addressing. This is done by writing and reading a set of Address, Data and
Command Registers. The following registers provide indirect access to the Rule Memory:
Rule Indirect Address Register,
Rule Indirect Data Register, and
Rule Indirect Command Register.
The following registers provide indirect access to the E-RAM:
E-RAM Indirect Address Register,
E-RAM Indirect Data Register, and
E-RAM Indirect Command Register.
Base 3 addresses
Base 2 addresses
Base 1 addresses
Base 0 addresses
Regisfor
Channel
0
Regisfor
Channel
1
Regisfor
Channel
2
Regisfor
Channel
3
Regisfor
Channel
31
no offset from
base addresses
CH1
’
s offsets
from bases
CH2
’
s offsets
from bases
CH3
’
s offsets
from bases
CH31
’
s offsets
from bases
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