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| 型號(hào)： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 48/162頁 |
| 文件大小： | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
51
PM2329 ClassiPI Network Classification Processor Datasheet
2.4.2 Extended RAM (E-RAM) Interface
The capabilities of the PM2329 can be enhanced significantly by the addition of the Extended RAM (E-
RAM). The PM2329 E-RAM interface is designed to connect directly to a bank of synchronous pipelined
SRAMs. The E-RAM stores Control Words (C-Words) and Data Words (D-Words) corresponding to each
on-chip Rule.
With the E-RAM connected, the PM2329 (or a cascade of PM2329 devices) works in the extended mode
of operation. This mode allows powerful OC sequencing capabilities in addition to storage of statistics and
aging information on a per-OC or per-connection basis. The E-RAM data can be automatically updated by
the PM2329 based upon the results of OC processing. The E-RAM can also provide a fast user-defined
lookup based on the results of an OC match.
The E-RAM interface memory address bus EMA[16:0] is connected to the C-Word and D-Word E-RAM
memory devices
’
address bus. The E-RAM interface control word data bus (ECD[31:0]) is connected to
the C-Word memory device
’
s data bus. In the cascade configuration, the EMA bus from all PM2329
devices are connected in parallel to all the memory buses of the C-Word and D-Word memory devices. The
ECD bus from all PM2329 devices are tied in parallel together and to the C-Word memory data bus.
The E-RAM interface data word data bus (EDD[31:0]) is connected to the D-Word memory device
’
s data
bus. In the cascade configuration, the EDD bus from each PM2329 device is connected to the data bus of
the corresponding D-Word memory device.
The E-RAM interface chip enable (EMCE*) and output enable (EMOE*) signals are always driven by the
primary device. Regardless of the configuration (single or cascade), the EMCE* and EMOE* signals of the
primary PM2329 device are tied to the corresponding chip enable signals and output enable signals of the
C-Word and D-Word E-RAM devices. In the cascade configuration, the EMCE* and EMOE* signals of
the secondary PM2329 devices are left unconnected.
The E-RAM interface write enable for the C-Word memory device (ECWE*) is connected from the
primary PM2329 device only to the write enable of the C-Word memory device. In the cascade
configuration, the ECWE* signals of all secondary PM2329 devices are left unconnected.
The E-RAM interface write enable for the D-Word memory device (EDWE*) is connected to the write
enable of the D-Word memory device. In the cascade configuration, the EDWE* signals of each PM2329
device is connected to the write enable signal of the corresponding D-Word memory device.
In the non-cascade configuration, the Bus Request (CEMRQ) signal can be left unconnected. In the
cascade configuration, the CEMRQ signals of every PM2329 device in the array are tied together.
The E-RAM width, depth and organization are all highly flexible through programmable registers. The
interface can handle a maximum E-RAM size of 128K words by 256 bits/word. The access times of the E-
RAM devices depends on the SCLK frequency as well as the number of PM2329 devices in cascade, since
they load the memory data bus. Moreover, the loading of the C-Word SRAM is not the same as that of the
D-Word SRAM, as explained in
Section 2.5
. The table below gives typical access times expected, but
these may change depending on board design and operating conditions.
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