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Document ID: PMC-2010146, Issue 4
96
PM2329 ClassiPI Network Classification Processor Datasheet
4.2.2.8 E-RAM Indirect Address Register (EIAR; 8228h)
Access Mode: Read/Write, Global
This register is used to specify the indirect read/write address of the E-RAM location to be accessed.
Level
In case the E-Word is larger than the physical width of the E-RAM, in one indirect read or write
operation of the E-RAM, the number of 32-bit words read or written will be determined by the E-RAM
Width. The Level field thus provides a means to access the other parts of the E-Word.
The Level is programmed as
00
Level 0
01
Level 1
10
Level 2
11
Level 3
Note that the results returned in the Data FIFO correspond to level 0 only. Exception to this rule is in the
case of a single E-RAM device where both the ECD and EDD buses are connected in parallel to the
same memory device. In this case, D-Word 0 (at Level 1) will be returned in the Data FIFO. Higher
levels in all cases must be accessed by the processor using E-RAM indirect addressing mechanism. See
E-RAM Configuration Register for more details.
When the Auto-increment mode select bit enables increment of the level field, the PM2329 will
increment the level field depending on the depth of E-Word in the E-RAM. If depth is 1, Level field is
not incremented. If depth is 2 Level field is incremented from 0 to 1 and then rolls over. If depth is 4,
Level field is incremented from 0 to 3 and then rolls over. If Level is programmed to an invalid value,
e.g., Level 2 when depth is 2, it will count up to 3 and then roll over.
E-Word Address
The location of the E-Word in the E-RAM to be written or read.
Bit
Range
63:24
23:22
21:17
16:0
Size
40
2
5
17
Name
Value after
Reset
Undefined
00
Undefined
0 0000h
(Reserved)
Level
(Reserved)
E-Word Address