參數資料
型號: PM2329
英文描述: Telecommunication IC
中文描述: 通信集成電路
文件頁數: 56/162頁
文件大?。?/td> 1581K
代理商: PM2329
Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
Internal Use
Document ID: PMC-2010146, Issue 4
59
PM2329 ClassiPI Network Classification Processor Datasheet
3.1.2 Data Flow
This section presents a brief overview of the data flow of a packet as it is processed. Details of packet
processing are discussed in later sections of this chapter.
Figure 15 illustrates the data flow for the PM2329 during normal operation. The data flow in the device
can be split into three phases:
Packet Transfer Phase
OC Processing Phase
Result Phase
Packet Transfer Phase
During the Packet Transfer Phase, the packet data and associated control information is transferred to the
device, over the PM2329
s system interface. It can be loaded into the PM2329 by a Packet Source (PS), or
directly by the external processor.
The packets are stored in the PM2329 Packet Input Buffer--an input FIFO which is the first element in the
data path inboard from the system interface.
Figure 16 Simplified Data Flow
The Packet Input Buffer
s physical size is 256 bytes deep times the total number of channels supported by
the PM2329 (256 x 32 bytes). A Packet Source can load the Packet Input Buffer using either a single write
port (the Packet Buffer Input Register, or PBIR), or alternatively with SRAM-like addressing, wherein a
block memory transfer mechanism is utilized in which the destination address increments.
In single-channel mode, the Packet Input Buffer acts like a FIFO for multiple packets. In multi-channel
mode, several packets may be transferred collectively into the Packet Input Buffer. If a cascade
PM2329
Field Extraction Engine
S
ctl info
Policy
Search
Engine
Control
Unit
Packet
Input
Buffer
E-RAM INTERFACE
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