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參數(shù)資料
| 型號： | PM2329 |
| 英文描述： | Telecommunication IC |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 91/162頁 |
| 文件大?。?/td> | 1581K |
| 代理商： | PM2329 |
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Proprietary and Confidential to PMC-Sierra, Inc and for its Customers
’
Internal Use
Document ID: PMC-2010146, Issue 4
94
PM2329 ClassiPI Network Classification Processor Datasheet
4.2.2.7 E-RAM Indirect Command Register (EICR; 8220h)
Access Mode: Read/Write, Global
Read/Write Data Enable
This field enables or disables reading or writing to each of the 32-bit physical E-RAMs, which may be
up to (32 x8) 256 bits wide. When a bit is
’
1
’
, it enables the corresponding E-RAM access. When a bit is
’
0
’
, the corresponding E-RAM access is disabled. The higher bit (bit 15) is for E-RAM Indirect Data
Register 0, and the lowest bit (bit 8) is for E-RAM Indirect Data Register 7. For example, programming
a value of
’
01101011
’
will enable writes to E-RAMs 1, 2, 4, 6 and 7 only. See Figure 2.8 for ERAM #
reference description.
Read/Write Data Enable bits in the E-RAM Indirect Command Register have a specific assignment for
each device as determined by its CID #, it controls the C-Word and/or D-Word connected to that device
regardless of the type of D-Word programming. This field is independent of D-Word type or depth, in
other words if a Read/Write Data Enable bit is disabled, all corresponding read/write access associated
with that E-RAM will be disabled. This field is applicable for E-RAM indirect operation only, OC
Sequencing controlled accesses are not qualified by this field.
Auto Increment Mode Select
If this bit is
‘
0
’
, increment operation is performed on the E-RAM address value only. If this bit is
‘
1
’
, the
Level value is also incremented in addition to the E-RAM address value. See Level field description for
further explanation.
Auto Increment Enable
This bit is written with
’
1
’
when a block of data needs to be transferred to or from the E-RAM. After the
read or write operation, the E-RAM Indirect Address Register is automatically incremented to point to
the next memory location (post increment).
If this bit is
‘
0
’
, the E-RAM Indirect Address Register is unchanged after a read or write operation to the
E-RAM Memory.
Bit
Range
63:16
15:8
7
6
5
4:2
1
0
Size
48
8
1
1
1
3
1
1
Name
Value after
Reset
Undefined
00h
Undefined
0
0
000
Undefined
1
(Reserved)
Read/Write Data Enable
(Reserved)
Auto Increment Mode Select
Auto Increment Enable
Trigger
(Reserved)
Register Set Ready (RO)
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