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參數(shù)資料
| 型號(hào)： | T7630 |
| 廠(chǎng)商： | Lineage Power |
| 英文描述： | Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器) |
| 中文描述： | 雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ）（雙個(gè)T1/E1 5.0V短距離通信終端器） |
| 文件頁(yè)數(shù)： | 10/210頁(yè) |
| 文件大?。?/td> | 3075K |
| 代理商： | T7630 |
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Table of Contents
(continued)
Table
Page
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
10
Lucent Technologies Inc.
Table 142. ET1 Remote End Errored Event Enable Register (FRM_PR15) (66F; C6F) ..................................... 169
Table 143. NT1 Errored Event Enable Register (FRM_PR16) (670; C70)........................................................... 169
Table 144. NT1 Remote End Errored Event Enable Registers
(FRM_PR17—FRM_PR18) ((671—672);(C71—C72))...................................................................................... 169
Table 145. Automatic AIS to the System and Automatic Loopback Enable Register (FRM_PR19) (673; C73) .. 170
Table 146. Transmit Test Pattern to the Line Enable Register (FRM_PR20) (674; C74)..................................... 170
Table 147. Framer FDL Control Command Register (FRM_PR21) (675; C75) ................................................... 171
Table 148. Framer Transmit Line Idle Code Register (FRM_PR22) (676; C76)................................................... 171
Table 149. Framer System Stuffed Time-Slot Code Register (FRM_PR23) (677; C77)...................................... 171
Table 150. Primary Time-Slot Loopback Address Register (FRM_PR24) (678; C78)......................................... 172
Table 151. Loopback Decoding of Bits LBC[2:0] in FRM_PR24, Bits 7—5 ........................................................ 172
Table 152. Secondary Time-Slot Loopback Address Register (FRM_PR25) (679; C79).................................... 173
Table 153. Loopback Decoding of Bits LBC[1:0] in FRM_PR25, Bits 6—5 ......................................................... 173
Table 154. Framer Reset and Transparent Mode Control Register (FRM_PR26) (67A, C7A)............................. 174
Table 155. Transmission of Remote Frame Alarm and CEPT
Automatic Transmission of A Bit = 1 Control Register (FRM_PR27) (67B, C7B)............................................... 175
Table 156. CEPT Automatic Transmission of E Bit = 0 Control Register (FRM_PR28) (67C; C7C).................... 176
Table 157. Sa4—Sa8 Source Register (FRM_PR29) (67D; C7D)....................................................................... 177
Table 158. Sa Bits Source Control for Bit 5—Bit 7 in FRM_PR29....................................................................... 177
Table 159. Sa4—Sa8 Control Register (FRM_PR30) (67E; C7E)....................................................................... 178
Table 160. Sa Transmit Stack (FRM_PR31—FRM_PR40) ((67F—688); (C7F—C88))....................................... 178
Table 161. SLC-96 Transmit Stack (FRM_PR31—FRM_PR40) ((67F—688); (C7F—C88))............................... 179
Table 162. Transmit SLC-96 FDL Format ............................................................................................................ 179
Table 163. CEPT Time Slot 16 X-Bit Remote Multiframe Alarm
and AIS Control Register (FRM_PR41)(689; C89)............................................................................................ 179
Table 164. Framer Exercise Register (FRM_PR42) (68A; C8A).......................................................................... 180
Table 165. Framer Exercises, FRM_PR42 Bit 5—Bit 0 (68A; C8A)..................................................................... 180
Table 166. DS1 System Interface Control and CEPT FDL Source Control Register (FRM_PR43) (68B; C8B).. 181
Table 167. Signaling Mode Register (FRM_PR44) (68C; C8C)........................................................................... 182
Table 168. CHI Common Control Register (FRM_PR45) (68D; C8D)................................................................. 183
Table 169. CHI Common Control Register (FRM_PR46) (68E; C8E) ................................................................. 184
Table 170. CHI Transmit Control Register (FRM_PR47) (68F; C8F)................................................................... 184
Table 171. CHI Receive Control Register (FRM_PR48) (690; C90).................................................................... 184
Table 172. CHI Transmit Time-Slot Enable Registers (FRM_PR49—FRM_PR52) ((691—694); (C91—C94))... 185
Table 173. CHI Receive Time-Slot Enable Registers (FRM_PR53—FRM_PR56) ((695—698); (C95—C98))... 185
Table 174. CHI Transmit Highway Select Registers (FRM_PR57—FRM_PR60) ((699—69C); (C99—C9C)) .... 185
Table 175. CHI Receive Highway Select Registers (FRM_PR61—FRM_PR64) ((69D—6A0); (C9D—CA0)).... 186
Table 176. CHI Transmit Control Register (FRM_PR65) (6A1; CA1)................................................................... 186
Table 177. CHI Receive Control Register (FRM_PR66) (6A2; CA2)................................................................... 186
Table 178. Auxiliary Pattern Generator Control Register (FRM_PR69) (6A5; CA5)............................................ 187
Table 179. Pattern Detector Control Register (FRM_PR70) (6A6; CA6)............................................................. 188
Table 180. Transmit Signaling Registers: DS1 Format
(FRM_TSR0—FRM_TSR23) ((6E0—6F7); (CE0—CF7))................................................................................. 189
Table 181. Transmit Signaling Registers: CEPT Format
(FRM_TSR0—FRM_TSR31) ((6E0—6FF); (CE0—CFF))................................................................................. 189
Table 182. FDL Register Set (800—80E); (E00—E0E)....................................................................................... 190
Table 183. FDL Configuration Control Register (FDL_PR0) (800; E00).............................................................. 191
Table 184. FDL Control Register (FDL_PR1) (801; E01) .................................................................................... 191
Table 185. FDL Interrupt Mask Control Register (FDL_PR2) (802; E02) ............................................................ 192
Table 186. FDL Transmitter Configuration Control Register (FDL_PR3) (803; E03) ........................................... 193
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