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參數(shù)資料
| 型號(hào)： | T7630 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器) |
| 中文描述： | 雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ）（雙個(gè)T1/E1 5.0V短距離通信終端器） |
| 文件頁(yè)數(shù)： | 38/210頁(yè) |
| 文件大?。?/td> | 3075K |
| 代理商： | T7630 |
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Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
38
L Lucent Technologies Inc.
Line Interface Unit: Jitter Attenuator
(continued)
Jitter Accommodation
The minimum jitter accommodation of the jitter attenuator occurs when the SYSCK frequency and the input clock’s
long-term average frequency are at their extreme frequency tolerances. When the jitter attenuator is used in the
LIU transmit path, the minimum accommodation is 28 UI peak-to-peak at the highest jitter frequency of
15 kHz. Typical receiver jitter accommodation curves including the jitter attenuator in the LIU receive path are given
in Figures 12 and 14.
When the jitter attenuator is placed in the data path, a difference between the SYSCK/16 frequency and the incom-
ing line rate for receive applications, or the TCLK rate for transmit applications will result in degraded low-
frequency jitter accommodation performance. The peak-to-peak jitter accommodation (JApp) for frequencies from
above the corner frequency of the jitter attenuator (Fc) to approximately 100 Hz is given by the following equation:
where:
fdata = 1.544 MHz for DS1 or 2.048 MHz for E1,
for JABW0 = 0, fc = 3.8 Hz for DS1 or 10 Hz for E1,
and for JABW0 = 1, fc = 1.25 Hz for E1,
yfsysclk = SYSCK tolerance in ppm,
yfdata = data tolerance in ppm.
Note that for lower corner frequencies the jitter accommodation is more sensitive to clock tolerance than for higher
corner frequencies. When JABW0 = 1 and the jitter attenuator is used in the receive data path, the tolerance on
SYSCK should be tightened to ±20 ppm in order to meet the jitter accommodation requirements of TBR12/13 as
given in G.823 for line data rates of ±50 ppm.
Jitter Attenuator Enable (Transmit or Receive Path)
The jitter attenuator is placed in the LIU receive path by setting JAR = 1 (register LIU_REG3, bit 0). The jitter atten-
uator is selected in the LIU transmit path by setting JAT = 1 (register LIU_REG3, bit 1). When JAR = 1 and JAT = 1
or when JAR = 0 and JAT = 0, the jitter attenuator is disabled. Note that the power consumption increases slightly
on a per-channel basis when the jitter attenuator is active. The reset default case is JAR = JAT = 0.
JApp
64
2
---------------------------2
f
sysclk
f
data
π
f
c
–
(
)
f
data
–
UI
=
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