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參數(shù)資料
| 型號： | T7630 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器) |
| 中文描述： | 雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ）（雙個T1/E1 5.0V短距離通信終端器） |
| 文件頁數(shù)： | 72/210頁 |
| 文件大小： | 3075K |
| 代理商： | T7630 |
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Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
72
L Lucent Technologies Inc.
CEPT Time Slot 0 FAS/NOT FAS Control
Bits
(continued)
I
CEPT with CRC-4
1
, automatic transmission of
E bit = 0:
— Optionally, one transmitted E bit is set to 0 by the
transmit framer, as described in ITU Rec. G.704
Section 2.3.3.4, for each received errored CRC-4
submultiframe detected by the receive framer if
FRM_PR28 bit 3 = 1.
— Optionally, as described in ITU Rec. G.704 Sec-
tion 2.3.3.4, both E bits are set to 0 while in a
received loss of CRC-4 multiframe alignment
state
2
if FRM_PR28 bit 4 = 1.
— Optionally, when the 100 ms or 400 ms timer is
enabled and the timer has expired, as described
in ITU Rec. G.706 Section B.2.2, both E bits are
set to 0 for the duration of the loss of CRC-4 multi-
frame alignment state
2
if FRM_PR28 bit 5 = 1.
Otherwise, the E bits are transmitted to the line in the
1 state.
NOT FAS A-Bit (CEPT Remote Frame Alarm)
Sources
The A bit, as described in ITU Rec. G.704 Section
2.3.2 Table 4a/G.704, is the remote alarm indication bit.
In undisturbed conditions, this bit is set to 0 and trans-
mitted to the line. In the loss of frame alignment (LFA)
state, this bit may be set to 1 and transmitted to the line
as determined by register FRM_PR27. The A bit is set
to 1 and transmitted to the line for the following condi-
tions:
I
Setting the transmit A bit = 1 control bit by setting
register FRM_PR27 bit 7 to 1.
I
Optionally for the following alarm conditions as
selected through programming register FRM_PR27.
— The duration of loss of basic frame alignment as
described in ITU Rec. G.706 Section 4.1.1
3
, or
ITU Rec. G.706 Section 4.3.2
4
if register
FRM_PR27 bit 0 = 1.
— The duration of loss of CRC-4 multiframe align-
ment if register FRM_PR27 bit 2 = 1.
— The duration of loss of signaling time slot 16 multi-
frame alignment if register FRM_PR27 bit 1 = 1.
— The duration of loss of CRC-4 multiframe align-
ment after either the 100 ms or 400 ms timer
expires if register FRM_PR27 bit 3 = 1.
— The duration of receive Sa6_8hex
5
if register
FRM_PR27 bit 4 = 1.
— The duration of receive Sa6_Chex
5
if register
FRM_PR27 bit 5 = 1.
NOT FAS Sa-Bit Sources
6
The Sa bits, Sa4—Sa8, in the NOT FAS frame can be a
4 kbits/s data link to and from the remote end. The
sources and value for the Sa bits are:
I
The Sa source register FRM_PR29 bit 0—bit 4 if
FRM_PR29 bit 7—bit 5 = 000 (binary) and
FRM_PR30 bit 4—bit 0 = 11111 (binary).
I
The facility data link external input (TFDL) if register
FRM_PR29 bit 7 = 1 and register FRM_PR21
bit 6 = 1.
I
The internal FDL-HDLC if register FRM_PR29
bit 7 = 1 and register FRM_PR21 bit 6 = 0.
I
The Sa transmit stack if register FRM_PR29
bit 7—bit 5 are set to 01x (binary).
I
The CHI system interface if register FRM_PR29
bit 7—bit 5 are set to 001 (binary). This option
requires the received system data (RCHIDATA) to
maintain a biframe alignment pattern where (1)
frames containing Sa bit information have bit 2 of
time slot 0 in the binary 1 state and (2) these NOT
FAS frames are followed by frames not containing Sa
bit information, the FAS frames, which have bit 2 of
time slot 0 in the binary 0 state. This ensures the
proper alignment of the Sa received system data to
the transmit line Sa data. Whenever this requirement
is not met by the system, the transmit framer will
enter a loss of biframe alignment condition indicated
in the status register, FRM_SR1 bit 4, and then
search for the pattern. In the loss of biframe align-
ment state, transmitted line data is corrupted (only
when the system interface is sourcing Sa or Si data).
When the transmit framer locates a new biframe
alignment pattern, an indication is given in the status
registers and the transmit framer resumes normal
operations.
1. The receive E-bit processor will halt the monitoring of received E
bits during loss of CRC-4 multiframe alignment.
2. Whenever loss of frame alignment occurs, then loss of CRC-4
multiframe alignment is forced. Once frame alignment is estab-
lished, then and only then, is the search for CRC-4 multiframe
alignment initiated. The receive framer unit, when programmed for
CRC-4, can be in a state of LFA and LTS0MFA or in a state of
LTS0MFA only, but cannot be in a state of LFA only.
3. LFA is due to framing bit errors.
4. LFA is due to detecting 915 out of 1000 received CRC-4 errored
blocks.
5. See Table 41 Sa6 Bit Coding Recognized by the Receive Framer,
for a definition of this Sa6 pattern.
6. Whenever bits (e.g., Si, Sa, etc.) are transmitted from the system
transparently, FRM_PR29 must first be momentarily written to
001xxxxx (binary). Otherwise, the transmit framer will not be able
to locate the biframe alignment.
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