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| 型號(hào)： | T7630 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器) |
| 中文描述： | 雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ）（雙個(gè)T1/E1 5.0V短距離通信終端器） |
| 文件頁(yè)數(shù)： | 64/210頁(yè) |
| 文件大小： | 3075K |
| 代理商： | T7630 |
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Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
64
L Lucent Technologies Inc.
Frame Formats
(continued)
CEPT Time Slot 0 CRC-4 Multiframe Structure
The CRC-4 multiframe is in bit 1 of each NOT FAS frame. As described in ITU Rec. G.704 Section 2.3.3.1, where
there is a need to provide additional protection against simulation of the frame alignment signal, and/or where there
is a need for an enhanced error monitoring capability, then bit 1 of each frame may be used for a cyclic redundancy
check-4 (CRC-4) procedure as detailed below. The allocation of bits 1—8 of time slot 0 of every frame is shown in
Table 32 for the complete CRC-4 multiframe.
Table 32. ITU CRC-4 Multiframe Structure
Notes:
C1 to C4 = cyclic redundancy check-4 (CRC-4) bits.
E = CRC-4 error indication bits.
Sa4 to Sa8 = spare bits.
A = remote frame alarm (RFA) bit (active-high); referred to as the A bit.
The CRC-4 multiframe consists of 16 frames numbered 0 to 15 and is divided into two eight-frame submultiframes
(SMF), designated SMF-I and SMF-II that signifies their respective order of occurrence within the CRC-4 multi-
frame structure. The SMF is the CRC-4 block size (2048 bits). In those frames containing the frame alignment sig-
nal (FAS), bit 1 is used to transmit the CRC-4 bits. There are four CRC-4 bits, designated C1, C2, C3, and C4 in
each SMF. In those frames not containing the frame alignment signal (NOT FAS), bit 1 is used to transmit the 6-bit
CRC-4 multiframe alignment signal and two CRC-4 error indication bits (E). The multiframe alignment signal is
defined in ITU Rec. G.704 Section 2.3.3.4, as 001011. Transmitted E bits should be set to 0 until both basic frame
and CRC-4 multiframe alignment are established. Thereafter, the E bits should be used to indicate received errored
submultiframes by setting the binary state of one E bit from 1 to 0 for each errored submultiframe. The received E
bits will always be taken into account, by the receive E-bit processor
*
, even when the SMF that contains them is
found to be errored. In the case where there exists equipment that does not use the E bits, the state of the E bits
should be set to a binary 1 state.
* The receive E-bit processor will halt the monitoring of the received E bit during the loss of CRC-4 multiframe alignment.
Multiframe
Submultiframe
(SMF)
Frame
Number
Bits
1
2
0
1
0
1
0
1
0
1
3
0
A
0
A
0
A
0
A
4
1
5
1
6
0
7
1
8
1
I
0
1
2
3
4
5
6
7
C1
0
C2
0
C3
1
C4
0
Sa4
1
Sa4
1
Sa4
1
Sa4
Sa5
1
Sa5
1
Sa5
1
Sa5
Sa6
0
Sa6
0
Sa6
0
Sa6
Sa7
1
Sa7
1
Sa7
1
Sa7
Sa8
1
Sa8
1
Sa8
1
Sa8
II
8
9
10
11
12
13
14
15
C1
1
C2
1
C3
E
C4
E
0
1
0
1
0
1
0
1
0
A
0
A
0
A
0
A
1
1
0
1
1
Sa4
1
Sa4
1
Sa4
1
Sa4
Sa5
1
Sa5
1
Sa5
1
Sa5
Sa6
0
Sa6
0
Sa6
0
Sa6
Sa7
1
Sa7
1
Sa7
1
Sa7
Sa8
1
Sa8
1
Sa8
1
Sa8
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