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參數(shù)資料
| 型號(hào)： | T7630 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器) |
| 中文描述： | 雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ）（雙個(gè)T1/E1 5.0V短距離通信終端器） |
| 文件頁(yè)數(shù)： | 26/210頁(yè) |
| 文件大小： | 3075K |
| 代理商： | T7630 |
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Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
26
L Lucent Technologies Inc.
Line Interface Unit: Receive
(continued)
Jitter Accommodation and Jitter Transfer
Without the Jitter Attenuator
The RLIU is designed to accommodate large amounts
of input jitter. The RLIU’s jitter performance exceeds
the requirements shown in the RLIU specification
Table 5 and Table 6. Typical receiver performance with-
out the jitter attenuator in the path is shown in
Figures 6—9. Typical receiver performance with the jit-
ter attenuator is given in Figures 12—15. Jitter transfer
is independent of input ones density on the line inter-
face.
Receive Line Interface Configuration Modes
Zero Substitution Decoding (CODE)
When single-rail operation is selected with DUAL = 0
(register LIU_REG3, bit 3), the LIU B8ZS/HDB3 zero
substitution decoding can be selected via the CODE bit
(register LIU_REG3, bit 2). If CODE = 1, the B8ZS/
HDB3 decoding function is enabled in the receive path.
Decoded receive data appears at the internal LIU-to-
framer RPD interface (RPD-LIU). Code violations,
including BPVs, appear at the internal LIU-to-framer
RND_BPV interface (RND-LIU). If CODE = 0, the
receive data is passed unaltered to RPD-LIU, and all
bipolar violations (such as two consecutive ones if the
same polarity) appear at RND-LIU. The default configu-
ration is single-rail, DUAL = 0, with the decoding active,
CODE = 1.
If DUAL = 0, the receive framer must be programmed to
the single-rail mode and the receive framer’s internal
LIU-to-framer RPD input will be the receive data port. If
DUAL = 0, then the receive framer’s bipolar violation
count will increment by one whenever the internal LIU-
to-framer RND_BPV signal is one. The bipolar violation
count is incremented on the rising edge of the receive
framer’s RLCK clock signal.
Receive Line Interface Unit (RLIU) Alarms
Analog Loss of Signal (ALOS) Alarm
. An analog sig-
nal detector monitors the receive signal amplitude and
reports its status in the ALOS alarm bit ALOS (register
LIU_REG0, bit 0). ALOS is indicated (ALOS = 1) if the
amplitude at the RRING and RTIP inputs drops below a
voltage approximately 18 dB below the nominal signal
amplitude. The ALOS alarm condition will clear when
the receive signal amplitude returns to a level greater
than 14 dB below normal. The ALOS alarm status bit
will latch the alarm and remain set until being cleared
by a read (clear on read). Upon the transition from
ALOS = 0 to ALOS = 1, a microprocessor interrupt will
be generated if the ALOS interrupt enable bit ALOSIE
(register LIU_REG1, bit 0) is set. The reset default is
ALOSIE = 0.
The ALOS circuitry provides 4 dB of hysteresis to pre-
vent alarm chattering. The time required to detect
ALOS is selectable. When ALTIMER = 0 (register
LIU_REG4, bit 0), ALOS is declared between 1 ms and
2.6 ms after losing signal as required by I.431(3/93)
and ETS-300-233 (5/94). If ALTIMER = 1, ALOS is
declared between 10-bit and 255-bit symbol periods
after losing signal as required by G.775 (11/95). The
timing is derived from the SYSCK clock. The detection
time is independent of signal amplitude before the loss
condition occurs. Normally, ALTIMER = 1 would be
used only in E1 mode since no T1/DS1 standards
require this mode. In T1/DS1 mode, this bit should nor-
mally be zero. The reset default is ALTIMER = 0.
The behavior of the receiver RLIU outputs under ALOS
conditions is dependent on the loss shutdown (LOSSD)
control bit (register LIU_REG3, bit 4) in conjunction
with the receive alarm indication select (RCVAIS) con-
trol bit (register LIU_REG4, bit 1) as described in the
Loss Shutdown (LOSSD) and Receiver AIS (RCVAIS)
section on page 27. When operating on long-haul
loops, the receive input signal will routinely be well
below the 20 dB ALOS level. Therefore, when the
transmit equalization is programmed to any of the long-
haul settings shown in Table 8, the ALOS function is
completely disabled.
Digital Loss of Signal (DLOS) Alarm.
A (DLOS)
detector guarantees the received signal quality as
defined in the appropriate ANSI Bellcore and ITU
standards. The DLOS alarm is reported in the RLIU
alarm status register (register LIU_REG0, bit 1). For
DS1 operation, digital loss of signal (DLOS = 1) is indi-
cated if 100 or more consecutive zeros occur in the
receive data stream. The DLOS condition is deacti-
vated when the average ones density of at least 12.5%
is received in 100 contiguous pulse positions. The
DLOS alarm status bit will latch the alarm and remain
set until being cleared by a read (clear on read). The
LOSSTD control bit (register LIU_REG2, bit 2) selects
the conformance protocols for the DLOS alarm indica-
tion per Table 3. Setting LOSSTD = 1 adds an addi-
tional constraint that there are less than 15 consecutive
zeros in the DS1 data stream before DLOS is deacti-
vated. The reset default is LOSSTD = 0.
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