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參數(shù)資料
| 型號(hào)： | T7630 |
| 廠(chǎng)商： | Lineage Power |
| 英文描述： | Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器) |
| 中文描述： | 雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ）（雙個(gè)T1/E1 5.0V短距離通信終端器） |
| 文件頁(yè)數(shù)： | 125/210頁(yè) |
| 文件大小： | 3075K |
| 代理商： | T7630 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
125
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Microprocessor Interface
Overview
The T7630 device is equipped with a microprocessor
interface that can operate with most commercially avail-
able microprocessors. The microprocessor interface
provides access to all the internal registers through a
12-bit address bus and an 8-bit data bus. Inputs
MPMODE and MPMUX (pins 74 and 76) are used to
configure this interface into one of four possible modes,
as shown in Table 63. The MPMUX setting selects
either a multiplexed (8-bit address/data bus, AD[7:0]) or
a demultiplexed (12-bit address bus, A[11:0] and an
8-bit data bus AD[7:0]) mode of operation. The
MPMODE setting selects the associated set of control
signals required to access a set of registers within the
device.
The microprocessor interface can operate at speeds up
to 33 MHz in interrupt-driven or polled mode without
requiring any wait-states. For microprocessors operat-
ing at greater than 33 MHz, the RDY_DTACK output
(pin 100) may be used to introduce wait-states in the
read/write cycles.
In the interrupt-driven mode, one or more device
alarms will assert the INTERRUPT output (pin 99) once
per alarm activation. After the microprocessor identifies
the source(s) of the alarm(s) (by reading the global
interrupt register) and reads the specific alarm status
registers, the INTERRUPT output will deassert. In the
polled mode, however, the microprocessor monitors
the various device alarm status by periodically reading
the alarm status registers within the line interface unit,
framer, and HDLC blocks without the use of INTER-
RUPT. In both interrupt and polled methods of alarm
servicing, the status registers within an identified block
will clear on a microprocessor read cycle only when the
alarm condition within that block no longer exists; oth-
erwise, the alarm status register bit remains set.
The powerup default states for the line interface unit,
framer, and the HDLC blocks are discussed in their
respective sections. All read/write registers within
these blocks must be written by the microprocessor on
system start-up to guarantee proper device functional-
ity.
Register addresses not defined in this data
sheet must not be written.
Details concerning the microprocessor interface con-
figuration modes, pinout definitions, clock specifica-
tions, register address map, I/O timing specifications,
and the I/O timing diagrams are described in the follow-
ing sections.
Microprocessor Configuration Modes
Table 63 highlights the four microprocessor modes
controlled by the MPMUX and MPMODE inputs (pins
76 and 74).
Table 63. Microprocessor Configuration Modes
* ALE_AS may be connected to ground in this mode.
The DTACK signal is asynchronous to the MPCLK signal.
Mode
MPMODE
MPMUX
Address/Data Bus
Generic Control, Data, and Output Pin Names
CS
,
AS
,
DS
, R/
W
, A[11:0], AD[7:0], INT,
DTACK
CS
,
AS
,
DS
, R
/W
, A[11:8], AD[7:0], INT,
DTACK
CS
,
ALE
,
RD
,
WR
, A[11:0], AD[7:0], INT, RDY
CS
,
ALE
,
RD
,
WR
, A[11:8], AD[7:0], INT, RDY
Mode 1
Mode 2
Mode 3
Mode 4
0
0
1
1
0
1
0
1
DEMUXed*
MUXed
DEMUXed*
MUXed
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