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參數(shù)資料
| 型號(hào)： | T7630 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器) |
| 中文描述： | 雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ）（雙個(gè)T1/E1 5.0V短距離通信終端器） |
| 文件頁(yè)數(shù)： | 183/210頁(yè) |
| 文件大小： | 3075K |
| 代理商： | T7630 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
183
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture
(continued)
CHI Common Control Register (FRM_PR45)
These bits define the common attributes of the CHI for TCHIDATA, TCHIDATAB, RCHIDATA, and RCHDATAB. The
default value of this register is 00 (hex).
Table 168. CHI Common Control Register (FRM_PR45) (68D; C8D)
Bit
0
Symbol
HFLF
Description
High-Frequency/Low-Frequency PLLCK Clock Mode.
A 0 enables the low-frequency
PLLCK mode for the divide down circuit in the internal phase-lock loop section (DS1
PLLCK = 1.544 MHz; CEPT PLLCK = 2.048 MHz). The divide down circuit will produce
an 8 kHz signal on DIV-PLLCK, pin 6 and pin 32. A 1 enables the high-frequency PLLCK
mode for the divide down circuit in the internal phase-lock loop section (DS1: PLLCK =
6.176 (4 x 1.544) MHz; CEPT: 8.192 (4 x 2.048) MHz). The divide down circuit will pro-
duce a 32 kHz signal on DIV-PLLCK.
Concentration Highway Clock Mode.
A 0 enables the CHI clock frequency and CHI
data rate to be equal. Function fo CMS =1 is reserved. This control bit affects both the
transmit and receive interfaces.
Concentration Highway Interface Data Rate Select.
Bits
CHI Data Rate
2 3
0 0
2.048 Mbits/s
0 1
4.096 Mbits/s
1 0
8.192 Mbits/s
1 1
Reserved
Concentration Highway Master Mode.
A 0 enables external system’s frame synchroni-
zation signal (TCHIFS) to drive the transmit path of the framer’s concentration highway
interface. A 1 enables the framer’s transmit concentration interface to generate a system
frame synchronization signal derived from the receive line interface. The framer’s system
frame synchronization signal is generated on the TCHIFS output pin. Applications using
the receive line clock as the reference clock signal of the system are recommended to
enable this mode and use the TCHIFS signal generated by the framer. The receive CHI
path is not affected by this mode.
Reserved.
Write to 0.
Highway Enable.
A 1 in this bit position enables transmission to the concentration high-
way. This allows the T7630 to be fully configured before transmission to the highway. A 0
forces the idle code as defined in register FRM_PR22 to be transmitted to the line in all
payload time slots and the transmit CHI pin is forced to a high-impedance state for all
CHI transmitted time slots.
1
CMS
2—3
CDRS0—
CDRS1
4
CHIMM
5—6
7
—
HWYEN
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