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參數(shù)資料
| 型號： | T7630 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器) |
| 中文描述： | 雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ）（雙個T1/E1 5.0V短距離通信終端器） |
| 文件頁數(shù)： | 7/210頁 |
| 文件大?。?/td> | 3075K |
| 代理商： | T7630 |
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Lucent Technologies Inc.
7
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Table of Contents
(continued)
Table
Page
Table 1. Pin Descriptions-Channel 1 and Channel 2..............................................................................................19
Table 2. Pin Descriptions-Global............................................................................................................................23
Table 3. Digital Loss of Signal Standard Select......................................................................................................27
Table 4. LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes)..................................27
Table 5. T1/DS1 LIU Receiver Specifications.........................................................................................................28
Table 6. CEPT LIU Receiver Specifications ...........................................................................................................29
Table 7. Transmit Line Interface Short-Haul Equalizer/Rate Control ......................................................................32
Table 8. DSX-1 Pulse Template Corner Points (from CB119, T1.102)...................................................................35
Table 9. DS1 Transmitter Specifications.................................................................................................................35
Table 10. CEPT Transmitter Specifications ............................................................................................................37
Table 11. Loopback Control....................................................................................................................................41
Table 12. SYSCK (16x, CKSEL = 1) Timing Specifications....................................................................................42
Table 13. SYSCK (1x, CKSEL = 0) Timing Specifications......................................................................................42
Table 14. Termination Components by Application.................................................................................................44
Table 15. AMI Encoding .........................................................................................................................................48
Table 16. DS1 ZCS Encoding.................................................................................................................................48
Table 17. DS1 B8ZS Encoding...............................................................................................................................49
Table 18. ITU HDB3 Coding...................................................................................................................................49
Table 19. T-Carrier Hierarchy..................................................................................................................................49
Table 20. D4 Superframe Format...........................................................................................................................52
Table 21. DDS Channel-24 Format ........................................................................................................................52
Table 22. SLC-96 Data Link Block Format .............................................................................................................54
Table 23. SLC-96 Line Switch Message Codes .....................................................................................................55
Table 24. Transmit and Receive SLC-96 Stack Structure.......................................................................................55
Table 25. Extended Superframe (ESF) Structure...................................................................................................56
Table 26. T1 Loss of Frame Alignment Criteria......................................................................................................57
Table 27. T1 Frame Alignment Procedures............................................................................................................58
Table 28. Robbed-Bit Signaling Options.................................................................................................................59
Table 29. SLC-96 9-State Signaling Format...........................................................................................................59
Table 30. 16-State Signaling Format......................................................................................................................60
Table 31. Allocation of Bits 1 to 8 of the FAS Frame and the NOT FAS Frame......................................................62
Table 32. ITU CRC-4 Multiframe Structure.............................................................................................................64
Table 33. ITU CEPT Time Slot 16 Channel Associated Signaling Multiframe Structure........................................70
Table 34. Transmit and Receive Sa Stack Structure...............................................................................................74
Table 35. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames...........................................77
Table 36. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels....................................77
Table 37. Associated Signaling Mode CHI 2-Byte Time-Slot Format for CEPT .....................................................77
Table 38. Red Alarm or Loss of Frame Alignment Conditions................................................................................82
Table 39. Remote Frame Alarm Conditions............................................................................................................82
Table 40. Alarm Indication Signal Conditions.........................................................................................................82
Table 41. Sa6 Bit Coding Recognized by the Receive Framer-Asynchronous Bit Stream.....................................84
Table 42. Sa6 Bit Coding Recognized by the Receive Framer-Synchronous Bit Stream.......................................85
Table 43. AUXP Synchronization and Clear Sychronization Process ....................................................................85
Table 44. Event Counters Definition.......................................................................................................................86
Table 45. Summary of the Deactivation of SSTSSLB and SSTSLLB Modes as a Function
of Activating the Primary Loopback Modes ..........................................................................................................89
Table 46. Register FRM_PR69 Test Patterns.........................................................................................................92
Table 47. Register FRM_PR70 Test Patterns.........................................................................................................93
Table 48. Automatic Enable Commands ................................................................................................................95
Table 49. On-Demand Commands.........................................................................................................................96
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