參數(shù)資料
型號(hào)： T7630
廠商： Lineage Power
英文描述： Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器)
中文描述： 雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ）（雙個(gè)T1/E1 5.0V短距離通信終端器）
文件頁(yè)數(shù)： 5/210頁(yè)
文件大?。?/td> 3075K
代理商： T7630
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Lucent Technologies Inc.
5
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Table of Contents
(continued)
Contents
Page
Operating Conditions ........................................................................................................................................... 207
Handling Precautions............................................................................................................................................207
Electrical Characteristics.......................................................................................................................................208
Logic Interface Characteristics...........................................................................................................................208
Power Supply Bypassing ......................................................................................................................................208
Outline Diagram ....................................................................................................................................................209
144-Pin TQFP....................................................................................................................................................209
Ordering Information .............................................................................................................................................210
Figures
Page
Figure 1. T7630 Block Diagram (One of Two Channels).........................................................................................14
Figure 2. T7630 Block Diagram: Receive Section (One of Two Channels).............................................................16
Figure 3. T7630 Block Diagram: Transmit Section (One of Two Channels).............................................................17
Figure 4. Pin Assignment........................................................................................................................................18
Figure 5. Block Diagram of Line Interface Unit: Single Channel .............................................................................25
Figure 6. T1/DS1 Receiver Jitter Accommodation Without Jitter Attenuator...........................................................30
Figure 7. T1/DS1 Receiver Jitter Transfer Without Jitter Attenuator........................................................................30
Figure 8. CEPT/E1 Receiver Jitter Accommodation Without Jitter Attenuator........................................................31
Figure 9. CEPT/E1 Receiver Jitter Transfer Without Jitter Attenuator.....................................................................31
Figure 10. DSX-1 Isolated Pulse Template .............................................................................................................34
Figure 11. ITU-T G.703 Pulse Template..................................................................................................................36
Figure 12. T1/DS1 Receiver Jitter Accommodation with Jitter Attenuator ..............................................................39
Figure 13. T1/DS1 Jitter Transfer of the Jitter Attenuator........................................................................................39
Figure 14. CEPT/E1 Receiver Jitter Accommodation with Jitter Attenuator............................................................40
Figure 15. CEPT/E1 Jitter Transfer of the Jitter Attenuator.....................................................................................40
Figure 16. Line Termination Circuitry ......................................................................................................................43
Figure 17. T7630 Line Interface Unit Approximate Equivalent Analog I/O Circuits.................................................45
Figure 18. Block Diagram of Framer Line Interface.................................................................................................46
Figure 19. Transmit Framer TLCK to TND, TPD and Receive Framer RND, RPD to RLCK Timing........................47
Figure 20. T1 Frame Structure................................................................................................................................50
Figure 21. T1 Transparent Frame Structure............................................................................................................51
Figure 22. T7630 Facility Data Link Access Timing of the Transmit and Receive Framer Sections........................53
Figure 23. Fs Pattern SLC-96 Superframe Format.................................................................................................53
Figure 24. ITU 2.048 Basic Frame, CRC-4 Multiframe, and Channel Associated Signaling Multiframe
Structures.............................................................................................................................................................61
Figure 25. CEPT Transparent Frame Structure.......................................................................................................62
Figure 26. Receive CRC-4 Multiframe Search Algorithm Using the 100 ms Internal Timer ...................................67
Figure 27. Receive CRC-4 Multiframe Search Algorithm for Automatic, CRC-4/Non-CRC-4
Equipment Interworking as Defined by ITU (From ITU Rec. G.706, Annex B.2.2 - 1991)....................................69
Figure 28. Facility Data Link Access Timing of the Transmit and Receive Framer Sections in the CEPT Mode.....73
Figure 29. Transmit and Receive Sa Stack Accessing Protocol..............................................................................75
Figure 30. Timing Specification for RFRMCK, RFRMDATA, and RFS in DS1 Mode...............................................78
Figure 31. Timing Specification for TFS, TLCK, and TPD in DS1 Mode.................................................................78
Figure 32. Timing Specification for RFRMCK, RFRMDATA, and RFS in CEPT Mode............................................79
Figure 33. Timing Specification for RFRMCK, RFRMDATA, RFS, and RSSFS in CEPT Mode..............................79
Figure 34. Timing Specification for RCRCMFS in CEPT Mode ..............................................................................80
Figure 35. Timing Specification for TFS, TLCK, and TPD in CEPT Mode ..............................................................80
Figure 36. Timing Specification for TFS, TLCK, TPD, and TSSFS in CEPT Mode.................................................80
Figure 37. Timing Specification for TFS, TLCK, TPD, and TCRCMFS in CEPT Mode...........................................81
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