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參數(shù)資料
| 型號(hào)： | T7630 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器) |
| 中文描述： | 雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ）（雙個(gè)T1/E1 5.0V短距離通信終端器） |
| 文件頁(yè)數(shù)： | 84/210頁(yè) |
| 文件大?。?/td> | 3075K |
| 代理商： | T7630 |
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Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator II)
84
L Lucent Technologies Inc.
Alarms and Performance Monitoring
(continued)
9. The CEPT
continuous E-bit
alarm (CREBIT)
(FRM_SR2 bit 2).
I
CREBIT is asserted when the receive framer
detects:
— Five consecutive seconds where each 1 second
interval contains
≥
991 received E bits = 0 events.
— Simultaneously no LFA occurred.
— Optionally, no remote frame alarm (A bit = 1) was
detected if register FRM_PR9 bit 0, bit 4, and bit 5
are set to 1.
— Optionally, neither Sa6-F
hex
nor Sa6-E
hex
codes
were detected if register FRM_PR9 bit 0, bit 4,
and bit 6 are set to 1.
— The five second timer is started when:
— CRC-4 multiframe alignment is achieved.
— And optionally, A = 0 is detected if register
FRM_PR9 bit 0, bit 4, and bit 5 are set to 1.
— And optionally, neither Sa6
_
F
hex1
nor Sa6
_
E
hex*
is
detected if register FRM_PR9 bit 0, bit 4, and bit 6
are set to 1.
I
The five second counter is restarted when:
— LFA occurs, or
— e990 E bit = 0 events occur in 1 second, or
— Optionally, an A bit = 1 is detected if register
FRM_PR9 bit 0, bit 4, and bit 5 are set to 1.
— Optionally, a valid Sa6 pattern 1111 (binary) or
Sa6 pattern 1110 (binary) code was detected if
register FRM_PR9 bit 0, bit 4, and bit 6 are
set to 1.
This alarm is disabled during loss of frame alignment
(LFA) or loss of CRC-4 multiframe alignment
(LTS0MFA).
10. Failed state alarm or the unavailable state alarm,
FRM_SR5 bit 3 and bit 7 and FRM_SR6 bit 3 and
bit 7.
This alarm is defined as the unavailable state at the
onset of ten consecutive severely errored seconds. In
this state, the receive framer inhibits incrementing of
the severely errored and errored second counters for
the duration of the unavailable state. The receive
framer deasserts the unavailable state condition at the
onset of ten consecutive errored seconds which were
not severely errored.
11. The 4-bit Sa6 codes (FRM_SR2 bit 3—bit 7).
Sa6 codes are asserted if three consecutive 4-bit pat-
terns have been detected. The alarms are disabled
when three consecutive 4-bit Sa6 codes have been
detected that are different from the pattern previously
detected. The receive framer monitors the Sa6 bits for
special codes described in ETS Draft prETS 300
233:1992 Section 9.2. The Sa6 codes are defined in
Tables 41 and 42. The Sa6 codes in Table 41 may be
recognized as an asynchronous bit stream in either
non-CRC-4 or CRC-4 modes as long as the receive
framer is in the basic frame alignment state. In the
CRC-4 mode, the receive framer can optionally recog-
nize the received Sa6 codes in Table 41 synchronously
to the CRC-4 submultiframe structure as long as the
receive framer is in the CRC-4 multiframe alignment
state (synchronous Sa6 monitoring can be enabled by
setting register FRM_PR10 bit 1 to 1). The Sa6 codes
in Table 42 are only recognized synchronously to the
CRC-4 submultiframe and when the receive framer is
in CRC-4 multiframe alignment. The detection of three
(3) consecutive 4-bit patterns are required to indicate a
valid received Sa6 code. The detection of Sa6 codes is
indicated in status register FRM_SR2 bit 3—bit 7.
Once set, any three-nibble (12-bit) interval that con-
tains any other Sa6 code will clear the current Sa6 sta-
tus bit. Interrupts may be generated by the Sa6 codes
given in Table 41.
Table 41. Sa6 Bit Coding Recognized by the
Receive Framer-Asynchronous
Bit Stream
* See Table 41, Sa6 Bit Coding Recognized by the Receive Framer,
for a definition of this Sa6 pattern.
Code
First Receive
Bit (MSB)
1
1
1
1
1
Last Received
Bit (LSB)
0
0
0
0
1
Sa6_8
hex
Sa6_A
hex
Sa6_C
hex
Sa6_E
hex
Sa6_F
hex
0
0
1
1
1
0
1
0
1
1
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