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參數(shù)資料
| 型號： | T7630 |
| 廠商： | Lineage Power |
| 英文描述： | Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)(雙 T1/E1 5.0V短距離通信終端器) |
| 中文描述： | 雙T1/E1的5.0V的短途終結(jié)者（終結(jié)者-Ⅱ）（雙個T1/E1 5.0V短距離通信終端器） |
| 文件頁數(shù)： | 153/210頁 |
| 文件大?。?/td> | 3075K |
| 代理商： | T7630 |
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Lucent Technologies Inc.
Lucent Technologies Inc.
153
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
Framer Register Architecture
(continued)
Table 92. Facility Event Register-2 (FRM_SR4) (604; C04)
Bit
0
Symbol
NFA
Description
New Frame Alignment.
A 1 indicates the receive framer established a new frame align-
ment which differs from the previous alignment.
Signaling Superframe Alignment.
A 1 indicates the receive framer has established the
signaling superframe alignment. In the SF modes (D4 and SLC-96) and CEPT modes,
this alignment is established only after primary frame alignment is determined.
T1 Line Loopback Off Code Detect.
A 1 indicates the receive framer detected the DS1
line loopback disable code in the payload. This code is defined in AT&T Technical Refer-
ence 62411 as a framed 001 pattern where the frame bit is inserted into the pattern.
New Biframe Alignment Established.
A 1 indicates the transmit framer has established
a biframe alignment for the transmission of transparent Si and or Sa bits from the system
data in the CEPT mode.
T1 Line Loopback On Code Detect.
A 1 indicates the receive framer detected the line
loopback enable code in the payload. This code is defined in AT&T Technical Reference
62411 as a framed 00001 pattern where the frame bit is inserted into the pattern.
New CEPT CRC-4 Multiframe Alignment.
A 1 indicates the CEPT CRC-4 multiframe
alignment in the receive framer has been established.
ESF FDL Payload Loopback On Code Detect.
A 1 indicates the receive framer
detected the line loopback enable code in the payload. This code is defined in ANSI
T1.403-1995 as a 1111111100101000 pattern in the facility data link, where the leftmost
bit is the MSB.
SLC-96 Receive FDL Stack Ready.
A 1 indicates that the receive FDL stack should be
read. This bit is cleared on read. Data in the receive FIFO must be read within 9 ms of
this interrupt. This bit is
not
updated during loss of frame or signaling superframe align-
ment.
ESF FDL Payload Loopback Off Code Detect.
A 1 indicates the receive framer
detected the line loopback disable code in the payload. This code is defined in ANSI
T1.403-1995 as a 1111111101001100 pattern in the facility data link, where the leftmost
bit is the MSB.
SLC-96 Transmit FDL Stack Ready.
A 1 indicates that the transmit FDL stack is ready
for new data. This bit is cleared on read. Data written within 9 ms of this interrupt will be
transmitted in the next SLC-96 D-bit superframe interval.
ESF FDL Line Loopback On Code Detect.
A 1 indicates the receive framer detected
the line loopback enable code in the payload. This code is defined in ANSIT1.403-1995
as a 1111111101110000 pattern in the facility data link, where the leftmost bit is the
MSB.
CEPT Receive Sa Stack Ready.
A 1 indicates that the receive Sa6 stack should be
read. This bit is clear on the first access to the Sa receive stack or at the beginning of
frame 0 of the CRC-4 double-multiframe. Data in the receive FIFO must be read within
4 ms of this interrupt. This bit is
not
updated during LFA.
FDL-LLBOFF
ESF FDL Line Loopback Off Code Detect.
A 1 indicates the receive framer detected
the line loopback disable code in the payload. This code is defined in ANSI T1.403-1995
as a 1111111100011100 pattern in the facility data link, where the leftmost bit is the
MSB.
TSaSR
CEPT Transmit Sa Stack Ready.
A 1 indicates that the transmit Sa stack is ready for
new data. This bit is cleared on the first access to the Sa transmit stack or at the begin-
ning of frame 0 of the CRC-4 double multiframe. Data written within 4 ms of this interrupt
will be transmitted in the next CRC-4 double multiframe interval.
1
SSFA
2
LLBOFF
BFA
3
LLBON
CMA
4
FDL-PLBON
SLCRFSR
5
FDL-PLBOF
SLCTFSR
6
FDL-LLBON
RSaSR
7
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