Table of Contents
(continued)
Table
Page
Preliminary Data Sheet
October 2000
T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)
8
Lucent Technologies Inc.
Table 50. Receive ANSICode ............................................................................................................................... 99
Table 51. Performance Report Message Structure................................................................................................ 99
Table 52. FDL Performance Report Message Field Definition............................................................................. 100
Table 53. Octet Contents and Definition.............................................................................................................. 100
Table 54. Receive Status of Frame Byte.............................................................................................................. 101
Table 55. HDLC Frame Format............................................................................................................................ 104
Table 56. Receiver Operation in Transparent Mode............................................................................................. 108
Table 57. Summary of the T7630’s Concentration Highway Interface Parameters.............................................. 113
Table 58. Programming Values for TOFF[2:0] and ROFF[2:0] when CMS = 0 .................................................... 118
Table 59. TAP Controller States in the Data Register Branch.............................................................................. 122
Table 60. TAP Controller States in the Instruction Register Branch..................................................................... 122
Table 61. T7630’s Boundary-Scan Instructions ................................................................................................... 123
Table 62. IDCODE Register................................................................................................................................. 124
Table 63. Microprocessor Configuration Modes .................................................................................................. 125
Table 64. Mode [1—4] Microprocessor Pin Definitions........................................................................................ 126
Table 65. Microprocessor Input Clock Specifications .......................................................................................... 127
Table 66. T7630 Register Address Map .............................................................................................................. 127
Table 67. Microprocessor Interface I/O Timing Specifications............................................................................. 128
Table 68. Register Summary ............................................................................................................................... 135
Table 69. Global Register Set (0x000—0x008) ................................................................................................... 139
Table 70. Primary Block Interrupt Status Register (GREG0) (000) ..................................................................... 140
Table 71. Primary Block Interrupt Enable Register (GREG1) (001) .................................................................... 140
Table 72. Global Loopback Control Register (GREG2) (002).............................................................................. 141
Table 73. Global Loopback Control Register (GREG3) (003).............................................................................. 141
Table 74. Global Control Register (GREG4) (004) .............................................................................................. 142
Table 75. Device ID and Version Registers (GREG5—GREG7) (005—007) ...................................................... 142
Table 76. Line Interface Units Register Set* ((400—40F); (A00—A0F)).............................................................. 143
Table 77. LIU Alarm Status Register (LIU_REG0) (400, A00)............................................................................. 144
Table 78. LIU Alarm Interrupt Enable Register (LIU_REG1) (401, A01) ............................................................. 144
Table 79. LIU Control Register (LIU_REG2) (402, A02)...................................................................................... 145
Table 80. LIU Control Register (LIU_REG3) (403, A03)...................................................................................... 145
Table 81. LOSSD and RCVAIS Control Configurations (Not Valid During Loopback Modes) (from Table 3) ...... 146
Table 82. LIU Register (LIU_REG4) (404, A04)................................................................................................... 146
Table 83. LIU Configuration Register (LIU_REG5) (405, A05) ............................................................................ 147
Table 84. Loopback Control................................................................................................................................. 147
Table 85. LIU Configuration Register (LIU_REG6) (406, A06) ............................................................................ 147
Table 86. Transmit Line Interface Short-Haul Equalizer/Rate Control (from Table 6)........................................... 148
Table 87. Framer Status and Control Blocks Address Range (Hexadecimal)...................................................... 148
Table 88. Interrupt Status Register (FRM_SR0) (600; C00)................................................................................ 149
Table 89. Facility Alarm Condition Register (FRM_SR1) (601; C01)................................................................... 150
Table 90. Remote End Alarm Register (FRM_SR2) (602; C02).......................................................................... 151
Table 91. Facility Errored Event Register-1 (FRM_SR3) (603; C03) ................................................................... 152
Table 92. Facility Event Register-2 (FRM_SR4) (604; C04) ................................................................................ 153
Table 93. Exchange Termination and Exchange Termination Remote
End Interface Status Register (FRM_SR5) (605; C05)...................................................................................... 154
Table 94. Network Termination and Network Termination Remote
End Interface Status Register (FRM_SR6) (606; C06)...................................................................................... 155
Table 95. Facility Event Register (FRM_SR7) (607; C07) ................................................................................... 156
Table 96. Bipolar Violation Counter Registers (FRM_SR8—FRM_SR9) ((608—609); (C08—C09)).................. 156
Table 97. Framing Bit Error Counter Registers (FRM_SR10—FRM_SR11) ((60A—60B); (C0A—C0B)) ........... 156